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降低采样缓冲区的数据缓冲量

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bacon
2025-08-24 17:58:22 +08:00
parent 7a54581b91
commit 1ea82ab72c
1 changed files with 17 additions and 9 deletions
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26
tb/shinTest/test_filter.py
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@@ -55,6 +55,7 @@ def convert_4b_2_5b(data):
def data_map_bit(bit_order, use_code = True):
#rom = [0xa5, 0x5a, 0x5a, 0xa5]
#print(bit_order)
rom = list(range(0, 255))
if use_code:
@@ -126,11 +127,11 @@ if __name__ == '__main__':
f = open("./tb/build/test_filter.vcd", "wt+", encoding="utf-8", newline="\n")
ratio = 100
multi_clk_num = 4 #(4, 8, 16)
multi_clk_num = 16 #(4, 8, 16)
sys_clk_val = 1
tx_ratio = ratio - 1
tx_ratio = ratio + 5
sim_stop_time = 550000 * multi_clk_num #ns
#噪声强度
@@ -180,8 +181,8 @@ if __name__ == '__main__':
det_edge = writer.register_var('easybus.sample', f'det_edge', 'wire', size=1, init=0)
det_edge_val = 0
sa_in_val = [0, ] * multi_clk_num * 3
ph_in_sa = [0, ] * multi_clk_num * 3
sa_in_val = [0, ] * multi_clk_num * 2
ph_in_sa = [0, ] * multi_clk_num * 2
chg_pos = 0
#phrase_limit_clk_idx = 0
@@ -261,6 +262,11 @@ if __name__ == '__main__':
ph_in_sa = ph_in_sa[1:] + [i, ]
det_edge_buf = [sa_in_val[i - 1] ^ sa_in_val[i] for i in range(1, len(sa_in_val))]
#print(sa_in_val, det_edge_buf, i)
if start_rx == 0:
if det_edge_buf[-1] == 1:
cur_ph = (ph_in_sa[-1] + (multi_clk_num >> 1) - 1) % multi_clk_num
writer.change(ph_reg, timestamp, cur_ph)
#输出edge
if det_edge_buf[-1] != det_edge_val:
@@ -269,7 +275,7 @@ if __name__ == '__main__':
#更新当前的phrase
#'''
check_pos = - multi_clk_num * 2 - 1
check_pos = - multi_clk_num - 1
if det_edge_buf[check_pos] == 1:
temp_ph = (ph_in_sa[check_pos] + (multi_clk_num >> 1) - 1) % multi_clk_num
@@ -289,30 +295,32 @@ if __name__ == '__main__':
if (start_rx == 1) and (i == 0):
if chg_pos == 0:
ref_saout_bit = data_map_bit(ref_sa_dout_idx)
#print(chg_pos, ref_sa_dout_idx, ref_saout_bit)
if output_sa_data:
ref_sa_bit.append(ref_saout_bit)
writer.change(ref_sa_dout, timestamp, ref_saout_bit)
ref_sa_dout_idx = ref_sa_dout_idx + 1
if output_sa_data:
sa_bit.append(sa_in_val[-multi_clk_num*2 - 1 + cur_ph])
sa_bit.append(sa_in_val[-multi_clk_num - 1 + cur_ph])
temp_sa_bit.append(sa_in_val[-multi_clk_num*2 - 1 + cur_ph])
temp_sa_bit.append(sa_in_val[-multi_clk_num - 1 + cur_ph])
writer.change(sa_dout, timestamp, temp_sa_bit[0])
writer.change(result_check, timestamp, temp_sa_bit[0] ^ ref_saout_bit)
temp_sa_bit = temp_sa_bit[1:]
elif chg_pos == -1:
ref_saout_bit = data_map_bit(ref_sa_dout_idx)
#print(chg_pos, ref_sa_dout_idx, ref_saout_bit)
if output_sa_data:
ref_sa_bit.append(ref_saout_bit)
writer.change(ref_sa_dout, timestamp, ref_saout_bit)
ref_sa_dout_idx = ref_sa_dout_idx + 1
if output_sa_data:
sa_bit.append(sa_in_val[-multi_clk_num*3 - 1 + cur_ph])
sa_bit.append(sa_in_val[-multi_clk_num*2 - 1 + cur_ph])
sa_bit.append(sa_in_val[-multi_clk_num - 1 + cur_ph])
temp_sa_bit.append(sa_in_val[-multi_clk_num*3 - 1 + cur_ph])
temp_sa_bit.append(sa_in_val[-multi_clk_num*2 - 1 + cur_ph])
temp_sa_bit.append(sa_in_val[-multi_clk_num - 1 + cur_ph])
writer.change(sa_dout, timestamp, temp_sa_bit[0])
writer.change(result_check, timestamp, temp_sa_bit[0] ^ ref_saout_bit)