SPI时序调整

2025-05-19 14:13:47 +08:00
parent c4daca834c
commit 1e606d28c2
3 changed files with 91 additions and 44 deletions
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -244,7 +244,8 @@ abstract class InterfaceBase extends Module{
      Seq(
        (addr === "h8".U )  -> cReg.busRate( 7,0 ),
        (addr === "h9".U )  -> cReg.spiSel,
-        (addr === "ha".U & isSlvMode)  -> sReg.localDevIndex,
+        (addr === "ha".U & isSlvMode)  -> sReg.localDevIndex(7,0),
+        (addr === "hb".U & isSlvMode)  -> sReg.localDevIndex(15,8),


        (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),