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SPI时序调整

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This commit is contained in:
Ruige Lee
2025-05-19 14:13:47 +08:00
parent c4daca834c
commit 1e606d28c2
3 changed files with 91 additions and 44 deletions
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3
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -244,7 +244,8 @@ abstract class InterfaceBase extends Module{
Seq(
(addr === "h8".U ) -> cReg.busRate( 7,0 ),
(addr === "h9".U ) -> cReg.spiSel,
(addr === "ha".U & isSlvMode) -> sReg.localDevIndex,
(addr === "ha".U & isSlvMode) -> sReg.localDevIndex(7,0),
(addr === "hb".U & isSlvMode) -> sReg.localDevIndex(15,8),
(addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),

83
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -43,8 +43,10 @@ abstract class SpiInterfaceBase extends Module{
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckPosedgeNext = ShiftRegisters(isSckPosedge, 2, false.B, true.B)
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1) //确定下降沿放数据到数据线上
val exReg = Reg(UInt(8.W))
val exRego = Reg(UInt(8.W))
val exRegi = Reg(UInt(8.W))
@@ -59,12 +61,13 @@ abstract class SpiInterfaceBase extends Module{
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & exReg === 1.U & byteSel === 3.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & exRegi === 1.U & byteSel === 3.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U)
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exReg
io.dataw := exRegi
io.addrSel :=
Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
val readData = RegEnable(io.datar, io.isEnR)
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -80,9 +83,9 @@ abstract class SpiInterfaceBase extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrSel := 0.U
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrSel := exReg
addrSel := exRegi
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrSel := Cat(exReg, addrSel(7,0))
addrSel := Cat(exRegi, addrSel(7,0))
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrSel := addrSel + 1.U
@@ -93,7 +96,7 @@ abstract class SpiInterfaceBase extends Module{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
spiCmd := "hFF".U
} .elsewhen( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 3.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := exReg
spiCmd := exRegi
}
@@ -107,7 +110,7 @@ class SSpiInterface extends SpiInterfaceBase{
sck := spi.sck
csn := spi.csn
spi.miso := exReg.extract(7)
spi.miso := exRego.extract(7)
when( shiftCSn(2) & ~shiftCSn(1) ){
bitSel := 0.U
@@ -117,18 +120,29 @@ class SSpiInterface extends SpiInterfaceBase{
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U & (byteSel === 1.U || byteSel === 2.U) ){ //CS为低，且SCK上跳补一拍 的第0bit
exReg := 0.U
} .elsewhen( isSpiWrite ){
exReg := 0.U
} .elsewhen( isSpiRead ){
exReg := io.datar
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(6 ,0), shiftMOSI(1) )
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftMOSI(1) )
}.otherwise{
exRegi := Cat( exRegi(6 ,0), shiftMOSI(1) )
}
}
//输出在SCK下降沿准备数据
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckNegedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){
when((byteSel === 1.U || byteSel === 2.U) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
exRego := io.datar
}
}.otherwise{
exRego := exRego << 1
}
}
}
class QSpiInterface extends SpiInterfaceBase{
@@ -136,7 +150,7 @@ class QSpiInterface extends SpiInterfaceBase{
sck := qspi.sck
csn := qspi.csn
qspi.miso := exReg(7, 4)
qspi.miso := exRego(7, 4)
qspi.isDirIn := isSpiWrite
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -147,18 +161,31 @@ class QSpiInterface extends SpiInterfaceBase{
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U & ( byteSel === 1.U || byteSel === 2.U) ){ //CS为低，且SCK上跳补一拍 的第0bit
exReg := 0.U
} .elsewhen( io.isEnW ){
exReg := 0.U
} .elsewhen( io.isEnR ){
exReg := io.datar
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(3,0), shiftMOSI(1) )
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftMOSI(1) )
}.otherwise{
exRegi := Cat( exRegi(3 ,0), shiftMOSI(1) )
}
}
//输出在SCK下降沿准备数据
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckNegedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){
when((byteSel === 1.U || byteSel === 2.U) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
exRego := readData
}
}.otherwise{
exRego := exRego << 4
}
}
}