From 1dee4519bbeda08a7f9ab209dba9eaf5699efe6b Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 16 Sep 2025 11:27:02 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=90=8C=E6=AD=A5=E5=AD=90?= =?UTF-8?q?=E6=8A=A5=E6=96=87A=EF=BC=9B=E9=AA=8C=E8=AF=81=E5=85=B3?= =?UTF-8?q?=E6=B3=A8=E7=82=B91=EF=BC=89=E5=8F=98=E5=8C=96=E5=A2=9E?= =?UTF-8?q?=E9=87=8F=E7=9A=84=E6=AD=A3=E8=B4=9F=E6=96=B9=E5=90=91=202?= =?UTF-8?q?=EF=BC=89deltafinal=E4=BF=AE=E6=AD=A3=E5=89=8D=E5=90=8E?= =?UTF-8?q?=E8=B7=A8=E8=B6=8A=E6=AD=A3=E8=B4=9F=203=EF=BC=89=E5=89=8D?= =?UTF-8?q?=E4=BB=BF=E7=9C=9F=E7=9A=84=E7=BB=BC=E5=90=88=E8=A1=8C=E4=B8=BA?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/SlaveParser.scala | 46 +++++++++++++++---- 1 file changed, 37 insertions(+), 9 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index ff83dba..e4ff481 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -81,8 +81,9 @@ abstract class SlaveParserBase extends Module with RequireAsyncReset{ val SUBMSG_OPERATOR_UNIREAD = 0.U val SUBMSG_OPERATOR_UNIWRITE = 1.U val SUBMSG_OPERATOR_UNIRDWR = 2.U + val SUBMSG_OPERATOR_SYNCA = "ha".U val SUBMSG_OPERATOR_INDEX = "hb".U - val SUBMSG_OPERATOR_SYNC = "hc".U + val SUBMSG_OPERATOR_SYNCC = "hc".U val SUBMSG_OPERATOR_BOARDREAD = "hd".U val SUBMSG_OPERATOR_BOARDWRITE = "he".U val SUBMSG_OPERATOR_BOARDRDWR = "hf".U @@ -802,7 +803,7 @@ trait SlaveParserSync{ this: SlaveParserBase => def subOp2(x:UInt) = ~x + 1.U val addr64_res = addr64_op1 + addr64_op2 - val addrConflict = WireDefault(VecInit(Seq.fill(4){false.B})) + val addrConflict = WireDefault(VecInit(Seq.fill(5){false.B})) dontTouch(addrConflict) assert( PopCount(addrConflict) <= 1.U ) @@ -811,13 +812,17 @@ trait SlaveParserSync{ this: SlaveParserBase => when( downRecParser.io.subMsgTailReq.fire ){ when( isDownRecPing ){ //override - when( downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 + when( + downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNCA || + downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNCC ) { //同步包 downSubMsgTailInfo(0).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } .otherwise{ //pong //override - when( downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) { //同步包 ) + when( + downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNCA || + downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNCC ) { //同步包 ) downSubMsgTailInfo(1).workCnt := downRecParser.io.subMsgTailReq.bits.workCnt + 1.U } } @@ -834,6 +839,7 @@ trait SlaveParserSync{ this: SlaveParserBase => val mstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主发从接时间差(中间变量) val deltaMstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主差从差时间差(中间变量) val deltaFinal = RegInit(0.U(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差 + val deltaFinalPre = RegInit(0.U(64.W)) //当前时间戳与主站时间差预记录 // recoTimeStamp = io.timeStamp + deltaFinal // recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp @@ -859,8 +865,10 @@ trait SlaveParserSync{ this: SlaveParserBase => //下行接收 val isSync = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNC ) | - ( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC ) + ( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNCA ) | + ( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNCC ) | + ( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNCA ) | + ( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNCC ) ) val syncCnt = RegInit(0.U(4.W)) @@ -911,7 +919,9 @@ trait SlaveParserSync{ this: SlaveParserBase => } } - when( RegNext(isSync, false.B) & ~isSync ){ + val shiftIsSync = ShiftRegisters(isSync, 3, false.B, true.B) + + when( shiftIsSync(0) & ~isSync ){ // deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1 addr64_op1 := Cat( Fill(32, mstDeltaTimeStamp(31)), mstDeltaTimeStamp) //组合逻辑 @@ -919,12 +929,30 @@ trait SlaveParserSync{ this: SlaveParserBase => addrConflict(2) := true.B //组合逻辑 deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑 - } .elsewhen( RegNext(RegNext(isSync, false.B), false.B) & ~RegNext(isSync, false.B) ){ + } .elsewhen( shiftIsSync(1) & ~shiftIsSync(0) ){ // deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑 addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑 addrConflict(3) := true.B //组合逻辑 - deltaFinal := addr64_res //时序逻辑 + deltaFinalPre := addr64_res //时序逻辑 + } .elsewhen( shiftIsSync(2) & ~shiftIsSync(1) ){ + when( + ( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNCC ) | + ( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNCC ) + ){ + deltaFinal := deltaFinalPre + } .elsewhen( + ( isDownRecPing & downSubMsgHeadInfo(0).devIndex === 0.U & downSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_SYNCA ) | + ( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNCA ) + ){ + addr64_op1 := deltaFinal //组合逻辑 + addr64_op2 := subOp2(deltaFinalPre) //组合逻辑 + addrConflict(4) := true.B //组合逻辑 + deltaFinal := MuxCase( deltaFinalPre, Seq( //时序逻辑 + ( addr64_res.asSInt < -10.S ) -> ( deltaFinal - 10.U ), + ( addr64_res.asSInt > 10.S ) -> ( deltaFinal + 10.U ), + ) ) + } }