diff --git a/src/main/scala/backBoard/DIn16.scala b/src/main/scala/backBoard/DIn16.scala
index 793102c..d96a992 100644
--- a/src/main/scala/backBoard/DIn16.scala
+++ b/src/main/scala/backBoard/DIn16.scala
@@ -135,13 +135,5 @@ with BackBoardSlvIn16{
     upReg(5) := digitalFilter(1)
   }
 
-  page15reg2 := 0.U
-  page15reg3 := 2.U
-  page15reg4 := 2.U
-  page15reg5 := 0.U
-  page15reg6 := 0.U
-  page15reg7 := 0.U
-  page15reg8 := 0.U
-  page15reg9 := 0.U
 }
 
diff --git a/src/main/scala/backBoard/Dout16.scala b/src/main/scala/backBoard/Dout16.scala
index 23e8983..97805e5 100644
--- a/src/main/scala/backBoard/Dout16.scala
+++ b/src/main/scala/backBoard/Dout16.scala
@@ -59,20 +59,6 @@ with BackBoardSlvOut16{
 
   }
 
-
-
-  page15reg2 := 6.U
-  page15reg3 := 0.U
-  page15reg4 := 4.U
-  page15reg5 := 2.U
-  page15reg6 := 0.U
-  page15reg7 := 0.U
-  page15reg8 := 0.U
-  page15reg9 := 0.U
-
-
-
-
   out := outPin
 
 }
diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 5c20db9..3fd19b4 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -4,6 +4,15 @@ import chisel3._
 import chisel3.util._
 
 class ManualParamBundle extends Bundle{
+  val data2 = UInt(8.W)
+  val data3 = UInt(8.W)
+  val data4 = UInt(8.W)
+  val data5 = UInt(8.W)
+  val data6 = UInt(8.W)
+  val data7 = UInt(8.W)
+  val data8 = UInt(8.W)
+  val data9 = UInt(8.W)
+
   val vendorID  = UInt( 16.W )
   val moduleID  = UInt( 16.W )
   val hwVersion = UInt( 16.W )
@@ -28,30 +37,18 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
     RegEnable( downRegTemp(1).extract(5+i), false.B, isCrcPass )
   }
 
-
-  val page15reg2 = WireDefault(0.U(8.W))
-  val page15reg3 = WireDefault(0.U(8.W))
-  val page15reg4 = WireDefault(0.U(8.W))
-  val page15reg5 = WireDefault(0.U(8.W))
-  val page15reg6 = WireDefault(0.U(8.W))
-  val page15reg7 = WireDefault(0.U(8.W))
-  val page15reg8 = WireDefault(0.U(8.W))
-  val page15reg9 = WireDefault(0.U(8.W))
-
   upReg(0) := Cat( statusPR.extract(0), statusRF, statusP, 0.U(1.W), statusPage )
   upReg(1) := Cat( customData(2), customData(1), customData(0), statusNone, statusSync, statusLE, statusER, statusPR.extract(1) )
 
   when( statusPage === 15.U ){
-    upReg(2) := page15reg2
-    upReg(3) := page15reg3
-
-    upReg(4) := page15reg4
-    upReg(5) := page15reg5
-
-    upReg(6) := page15reg6
-    upReg(7) := page15reg7
-    upReg(8) := page15reg8
-    upReg(9) := page15reg9
+    upReg(2) := param.data2
+    upReg(3) := param.data3
+    upReg(4) := param.data4
+    upReg(5) := param.data5
+    upReg(6) := param.data6
+    upReg(7) := param.data7
+    upReg(8) := param.data8
+    upReg(9) := param.data9
 
 
     upReg(10) := param.vendorID(7,0)
diff --git a/src/main/verilog/defineParam.v b/src/main/verilog/defineParam.v
index e1e4a2c..e91e170 100644
--- a/src/main/verilog/defineParam.v
+++ b/src/main/verilog/defineParam.v
@@ -1,3 +1,13 @@
+`define DATA2     8'h0
+`define DATA3     8'h0
+`define DATA4     8'h0
+`define DATA5     8'h0
+`define DATA6     8'h0
+`define DATA7     8'h0
+`define DATA8     8'h0
+`define DATA9     8'h0
+
+
 `define VENDORID  16'h1122
 `define MODULEID  16'h3344
 `define HWVERSION 16'h5566
diff --git a/src/main/verilog/di16_top.v b/src/main/verilog/di16_top.v
index 4285f87..cd026c4 100644
--- a/src/main/verilog/di16_top.v
+++ b/src/main/verilog/di16_top.v
@@ -286,6 +286,14 @@ DIn16 i_din16(
   .io_isLast(isLast_temp1),
   .io_DCIn(DCIn),
 
+  .param_data2(`DATA2),
+  .param_data3(`DATA3),
+  .param_data4(`DATA4),
+  .param_data5(`DATA5),
+  .param_data6(`DATA6),
+  .param_data7(`DATA7),
+  .param_data8(`DATA8),
+  .param_data9(`DATA9),
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),
diff --git a/src/main/verilog/do16_top.v b/src/main/verilog/do16_top.v
index c5cb911..dfc6b4c 100644
--- a/src/main/verilog/do16_top.v
+++ b/src/main/verilog/do16_top.v
@@ -292,6 +292,14 @@ DOut16 i_dout16(
   .io_isLast(isLast_temp1),
   .io_DCIn(DCIn),
 
+  .param_data2(`DATA2),
+  .param_data3(`DATA3),
+  .param_data4(`DATA4),
+  .param_data5(`DATA5),
+  .param_data6(`DATA6),
+  .param_data7(`DATA7),
+  .param_data8(`DATA8),
+  .param_data9(`DATA9),
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),
diff --git a/src/main/verilog/do16inv_top.v b/src/main/verilog/do16inv_top.v
index e4acc13..29ff338 100644
--- a/src/main/verilog/do16inv_top.v
+++ b/src/main/verilog/do16inv_top.v
@@ -292,6 +292,14 @@ DOut16 i_dout16(
   .io_isLast(isLast_temp1),
   .io_DCIn(DCIn),
 
+  .param_data2(`DATA2),
+  .param_data3(`DATA3),
+  .param_data4(`DATA4),
+  .param_data5(`DATA5),
+  .param_data6(`DATA6),
+  .param_data7(`DATA7),
+  .param_data8(`DATA8),
+  .param_data9(`DATA9),
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),
diff --git a/src/main/verilog/qei_top.v b/src/main/verilog/qei_top.v
index b75e32d..6a6a9f3 100644
--- a/src/main/verilog/qei_top.v
+++ b/src/main/verilog/qei_top.v
@@ -307,6 +307,14 @@ Qei i_qei(
   .io_lvdsSlv_downstream_rx_cdr_err(downstream_rx_cdr_err),
   .io_lvdsSlv_upstream_rx_cdr_err(upstream_rx_cdr_err),
 
+  .param_data2(`DATA2),
+  .param_data3(`DATA3),
+  .param_data4(`DATA4),
+  .param_data5(`DATA5),
+  .param_data6(`DATA6),
+  .param_data7(`DATA7),
+  .param_data8(`DATA8),
+  .param_data9(`DATA9),
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),
diff --git a/src/main/verilog/spi_top.v b/src/main/verilog/spi_top.v
index c542787..483b4ab 100644
--- a/src/main/verilog/spi_top.v
+++ b/src/main/verilog/spi_top.v
@@ -294,6 +294,14 @@ SpiSlv i_spiSlv(
   .io_isLast(isLast_temp1),
   .io_DCIn(DCIn),
 
+  .param_data2(`DATA2),
+  .param_data3(`DATA3),
+  .param_data4(`DATA4),
+  .param_data5(`DATA5),
+  .param_data6(`DATA6),
+  .param_data7(`DATA7),
+  .param_data8(`DATA8),
+  .param_data9(`DATA9),
   .param_vendorID(`VENDORID),
   .param_moduleID(`MODULEID),
   .param_hwVersion(`HWVERSION),