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Merge branch 'mp_eb_dev' into feature/syncSpi

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# Conflicts:
#	src/main/scala/backBoard/shin/SpiInterface.scala
This commit is contained in:
RuigeLee
2025-09-08 17:07:10 +08:00
parent c3c3a25e77 41d4805841
commit 1d5a257b58
123 changed files with 8627 additions and 767 deletions
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52
tb/shinTest/ShinTopSpiTb.v
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@@ -102,15 +102,28 @@ module ShinTopSpiTb(
reg _reset_deactive;
wire [(`ALL_DEV_NUM - 1):0] isSoftReset;
reg [(`ALL_DEV_NUM - 1):0] isSoftReset_reg;
generate
for( genvar i = 0; i < `ALL_DEV_NUM; i = i + 1 ) begin
always @(posedge clock or posedge reset) begin
if(reset) isSoftReset_reg[i] <= 1'b0;
else isSoftReset_reg[i] <= isSoftReset[i];
end
end
endgenerate
wire [`DEV_NUM:0] io_int_sig;
reg latch0;
reg latch1;
ShinTop s_ShinTop_Mst(
.clock(clock),
.reset(reset | isSoftReset[0]),
.reset(reset | isSoftReset_reg[0]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -157,7 +170,7 @@ ShinTop s_ShinTop_Mst(
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
.io_hwSerial(`HW_SERIAL),
.io_uniCode(0)
.io_uniCode(64'h0)
);
`include "slave_dev_def.vh"
@@ -165,7 +178,7 @@ ShinTop s_ShinTop_Mst(
`ifdef DEFINE_SLAVE_DEVICE
ShinTop s_ShinTop_slv0(
.clock(clock),
.reset(reset | isSoftReset[1]),
.reset(reset | isSoftReset_reg[1]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -216,7 +229,7 @@ ShinTop s_ShinTop_slv0(
ShinTop s_ShinTop_slv1(
.clock(clock),
.reset(reset | isSoftReset[2]),
.reset(reset | isSoftReset_reg[2]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -267,7 +280,7 @@ ShinTop s_ShinTop_slv1(
ShinTop s_ShinTop_slv2(
.clock(clock),
.reset(reset | isSoftReset[3]),
.reset(reset | isSoftReset_reg[3]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -318,7 +331,7 @@ ShinTop s_ShinTop_slv2(
ShinTop s_ShinTop_slv3(
.clock(clock),
.reset(reset | isSoftReset[4]),
.reset(reset | isSoftReset_reg[4]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -394,7 +407,8 @@ initial begin
$display("Time Out !!!");
$fclose(spidata_file);
$stop;
//$stop;
$finish;
end
initial begin
@@ -411,7 +425,7 @@ generate
initial begin
multiCLK[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin
#20
#10
;
end
forever begin #80 multiCLK[i] <= ~multiCLK[i]; end
@@ -425,8 +439,16 @@ initial
begin
spidata_file = $fopen("spi_trans_data.txt", "w");
if (!spidata_file) $display("文件打开失败");
$dumpfile("./tb/build/wave.vcd"); //生成的vcd文件名称
`ifdef VCS_COMPILE
$dumpfile("./generated/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, ShinTopSpiTb);//tb模块名称
`endif
`ifdef IVERILOG_COMPILE
$dumpfile("./generated/wave.fst"); //生成的fst文件名称
$dumpvars(0, ShinTopSpiTb);//tb模块名称
`endif
end
always @(posedge reset) begin
@@ -850,7 +872,7 @@ task f_write(input [31:0] logh, input [15:0] saddress, input [7:0] scmd, input [
end
endtask
task wait_comm_finished();
task wait_comm_finished(input [16:0] dev_idx);
begin:WAIT_COMM_FINISHED_CODE
real st;
integer is_run;
@@ -858,6 +880,7 @@ task wait_comm_finished();
st = $realtime;
is_run = 1;
`ifdef enable_wait_clear_int
txBuf[0] = 8'h00;
txBuf[1] = 8'h78;
txBuf[2] = `SPI_WRITE;
@@ -867,7 +890,7 @@ task wait_comm_finished();
txBuf[6] = 8'h00;
length = 8'h07;
idx = `IF_IQSPI(0);
idx = `IF_IQSPI(dev_idx);
#5
@(negedge sck)
@@ -879,7 +902,7 @@ task wait_comm_finished();
begin
end
`endif
while (is_run == 1) begin
txBuf[0] = 8'h00;
@@ -887,7 +910,7 @@ task wait_comm_finished();
txBuf[2] = `SPI_READ;
length = 8'h07;
idx = `IF_IQSPI(0);
idx = `IF_IQSPI(dev_idx);
#5
@(negedge sck)
@@ -1078,7 +1101,8 @@ initial begin
#1000000
$display("Testcase Finished! Time Out !!!");
$fclose(spidata_file);
$stop;
//$stop;
$finish;
end