Merge branch 'mp_eb_dev' into feature/syncSpi

# Conflicts:
#	src/main/scala/backBoard/shin/SpiInterface.scala

src/main/scala/backBoard/shin/SpiInterface.scala

@@ -47,8 +47,6 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   val exRego = RegInit(0.U(8.W))
   val exRegi = RegInit(0.U(8.W))
 
-
-
   val addrw  = RegInit(0.U(16.W))
   val addrr  = RegInit(0.U(16.W))
   val spiCmd = RegInit(0.U(1.W))
@@ -61,15 +59,12 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
   val byteSel = RegInit(0.U(12.W))
   val byteSelNext = RegNext(byteSel, 0.U(12.W))
 
-
   io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U
 
-
   io.dataw := exRegi
   io.addrr := addrr
   io.addrw := addrw
   
-
   when( shiftCSn(2) & ~shiftCSn(1) ){
     byteSel  := 0.U
   } .elsewhen( isSckPosedge & ~shiftCSn(1)  ){
@@ -118,8 +113,6 @@ class SSpiInterface extends SpiInterfaceBase{
     bitSel := bitSel + 1.U
   }
 
-
-
   //输入看SCK上升沿
   when( isSckPosedge & ~shiftCSn(1) ){
     when( bitSel === 0.U ){