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使用未使用4b/5b编码作为preamble

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This commit is contained in:
Ruige Lee
2025-03-04 10:58:59 +08:00
parent c64df6956d
commit 1c7eb4ce47
2 changed files with 10 additions and 10 deletions
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10
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -87,8 +87,8 @@ trait CDRInAxis{ this: CDRInBase =>
def HeaderByte: Int = 8
val ETH_PRE = "h55".U(8.W)
val ETH_SFD = "hD5".U(8.W)
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
val STATE_IDLE = 0.U
val STATE_HEADER = 1.U
@@ -114,7 +114,7 @@ trait CDRInAxis{ this: CDRInBase =>
stateNext :=
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
))
@@ -123,7 +123,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
bitCnt := 0.U
} .otherwise{
when( bitCnt === 9.U ){
@@ -133,7 +133,7 @@ trait CDRInAxis{ this: CDRInBase =>
}
}
when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
byteCnt := 0.U
} .elsewhen( bitCnt === 9.U ){
when( stateCurr === STATE_HEADER ){

10
src/main/scala/backBoard/ebus/CDROut.scala
View File

@@ -24,8 +24,8 @@ class CDROut extends Module{
def STATE_PREAMBLE = 1.U
def STATE_PAYLOAD = 2.U
val ETH_PRE = "h55".U(8.W)
val ETH_SFD = "hD5".U(8.W)
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, 0.U )
@@ -52,14 +52,14 @@ class CDROut extends Module{
when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
shiftData := Dualb4b5Encoder(ETH_PRE)
shiftData := ETH_PRE
} .otherwise{
when( bitCnt =/= 9.U ){
shiftData := shiftData << 1
} .otherwise{ //bitCnt === 9.U
when( stateCurr === STATE_PREAMBLE ){
shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array(
( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD),
shiftData := MuxCase( ETH_PRE, Array(
( byteCnt === 6.U ) -> ETH_SFD,
( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
))
} .elsewhen( stateCurr === STATE_PAYLOAD ){