add function demo

src/main/scala/backBoard/LocalRegisters.scala

@@ -6,16 +6,142 @@ import chisel3.util._
 
 
 
-
 trait LocalRegisters { this: BackBoardSlvBase =>
+  val led = IO(Output(UInt(3.W)))
+  val sw  = IO( Input(UInt(1.W)))
+
+
 
   val digitalDir = RegInit(0.U(32.W))
   val digitalOut = RegInit(0.U(32.W))
-  val digitalIn  = WireDefault(0.U(32.W))
+  val digitalIn  = RegInit(VecInit(Seq.fill(32){false.B}))
+  val digitalFilter = RegInit(0.U(2.W))
 
+
+  val clk100usCnt = RegInit(0.U(13.W))
+
+  when( clk100usCnt < 5000.U ){
+    clk100usCnt := clk100usCnt + 1.U
+  } .otherwise{
+    clk100usCnt := 0.U
+  }
+
+  for( i <- 0 until 32 ) {
+    val hiCnt = RegInit( 0.U( 7.W ) )
+    val loCnt = RegInit( 0.U( 7.W ) )
+    val toCnt = RegInit( 0.U( 7.W ) )
+
+    when( digitalFilter === "b00".U ){
+      digitalIn(i) := sw
+    } .elsewhen( digitalFilter === "b01".U ){
+      when( clk100usCnt === 5000.U ){
+        when( toCnt === 10.U ){
+          hiCnt := 0.U
+          loCnt := 0.U
+          toCnt := 0.U
+          when( hiCnt >= 8.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
+          when( loCnt >= 8.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
+        } .elsewhen( toCnt > 10.U ){
+          hiCnt := 0.U
+          loCnt := 0.U
+          toCnt := 0.U
+        } .otherwise{
+          when(sw === true.B)  { hiCnt := hiCnt + 1.U }
+          when(sw === false.B) { loCnt := loCnt + 1.U }
+          toCnt := toCnt + 1.U
+        }
+      }
+    } .elsewhen( digitalFilter === "b10".U ){
+      when( clk100usCnt === 5000.U ){
+        when( toCnt === 40.U ){
+          hiCnt := 0.U
+          loCnt := 0.U
+          toCnt := 0.U
+          when( hiCnt >= 32.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
+          when( loCnt >= 32.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
+        } .elsewhen( toCnt > 40.U ){
+          hiCnt := 0.U
+          loCnt := 0.U
+          toCnt := 0.U
+        } .otherwise{
+          when(sw === true.B)  { hiCnt := hiCnt + 1.U }
+          when(sw === false.B) { loCnt := loCnt + 1.U }
+          toCnt := toCnt + 1.U
+        }
+      }
+    } .elsewhen( digitalFilter === "b11".U ){
+      when( clk100usCnt === 5000.U ){
+        when( toCnt === 80.U ){
+          hiCnt := 0.U
+          loCnt := 0.U
+          toCnt := 0.U
+          when( hiCnt >= 64.U & digitalIn(i) === false.B){ digitalIn(i) := true.B }
+          when( loCnt >= 64.U & digitalIn(i) === true.B) { digitalIn(i) := false.B }
+        } .elsewhen( toCnt > 80.U ){
+          hiCnt := 0.U
+          loCnt := 0.U
+          toCnt := 0.U
+        } .otherwise{
+          when(sw === true.B)  { hiCnt := hiCnt + 1.U }
+          when(sw === false.B) { loCnt := loCnt + 1.U }
+          toCnt := toCnt + 1.U
+        }
+      }
+    }
+  }
+
+
+
+
+  
+  val pluseCnt = RegInit(0.U(32.W))
+
+  val pluseShift = ShiftRegisters( sw, 3, false.B, true.B )
+  when( ~pluseShift(2).asBool & pluseShift(1).asBool ){
+    pluseCnt := pluseCnt + 1.U
+  }
+
+  val pluseAutoCnt = RegInit(0.U(32.W))
+  val pluseAutoFre = RegInit(0.U(32.W))
+  when( clk100usCnt === 5000.U ){
+    pluseAutoCnt := 0.U
+    pluseAutoFre := pluseAutoCnt
+  } .elsewhen( ~pluseShift(2).asBool & pluseShift(1).asBool ){
+    pluseAutoCnt := pluseAutoCnt + 1.U
+  }
+
+  val qeiA = IO(Input(Bool()))
+  val qeiB = IO(Input(Bool()))
+
+  val qeiAShift = ShiftRegisters( qeiA, 2, false.B, true.B )
+  val qeiBShift = ShiftRegisters( qeiB, 3, false.B, true.B )
+
+  val qeiCnt = RegInit(0.U(32.W))
+  val qeiAutoCnt = RegInit(0.U(32.W))
+  val qeiAutoFre = RegInit(0.U(32.W))
+
+  when( ~qeiBShift(2) & qeiBShift(1) ){
+    qeiCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
+    qeiAutoCnt := Mux( qeiAShift(1), qeiCnt + 1.U, qeiCnt - 1.U )
+  }
+
+
+  when( clk100usCnt === 5000.U ){
+    qeiAutoCnt := 0.U
+    qeiAutoFre := qeiAutoCnt
+  } .elsewhen( ~qeiBShift(2) & qeiBShift(1) ){
+    qeiAutoCnt := Mux( qeiAShift(1), qeiAutoCnt + 1.U, qeiAutoCnt - 1.U )
+  }
+  
+  
   registersRD := Mux1H(Seq(
     (upStreamReq.io.latDat.bits.register === 0.U) -> digitalDir,
-    (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn,
+    (upStreamReq.io.latDat.bits.register === 1.U) -> digitalIn.asUInt,
+    (upStreamReq.io.latDat.bits.register === 2.U) -> digitalFilter,
+    (upStreamReq.io.latDat.bits.register === 3.U) -> pluseCnt,
+    (upStreamReq.io.latDat.bits.register === 4.U) -> pluseAutoFre,
+    (upStreamReq.io.latDat.bits.register === 5.U) -> qeiCnt,
+    (upStreamReq.io.latDat.bits.register === 6.U) -> qeiAutoFre,
   ))
 
   when( upStreamReq.io.latDat.fire & upStreamReq.io.latDat.bits.address(5,1) === io.localHost & upStreamReq.io.latDat.bits.address.extract(0) === 1.U ){
@@ -25,12 +151,26 @@ trait LocalRegisters { this: BackBoardSlvBase =>
     when(upStreamReq.io.latDat.bits.register === 1.U){
       digitalOut := upStreamReq.io.latDat.bits.data
     }
+    when(upStreamReq.io.latDat.bits.register === 2.U){
+      digitalFilter := upStreamReq.io.latDat.bits.data
+    }
+    when(upStreamReq.io.latDat.bits.register === 3.U){
+      pluseCnt := upStreamReq.io.latDat.bits.data
+    }
+    when(upStreamReq.io.latDat.bits.register === 4.U){
+      ;
+    }
+    when(upStreamReq.io.latDat.bits.register === 5.U){
+      qeiCnt := upStreamReq.io.latDat.bits.data
+    }
+    when(upStreamReq.io.latDat.bits.register === 6.U){
+      ;
+    }
   }
 
 
-  val led = IO(Output(UInt(3.W)))
-  val sw  = IO( Input(UInt(1.W)))
+
 
   led := digitalOut(2,0)
-  digitalIn := sw
+  // digitalIn := sw
 }