FSMC模块

src/main/scala/backBoard/ebus/FSMC.scala.bk

@@ -3,40 +3,38 @@ package BACK
 import chisel3._
 import chisel3.util._
 
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
 
 
 
 
-
-class FSMCSlvIO extends Bundle{
+class FSMCMemIO extends Bundle{
   val FSMC = new FSMC_Port_Bundle
 
-  val CDRIn  = Flipped(Valid(new CDRData))
-  val CDROut = Valid(new CDRData)
+  val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
+  val tld = new DecoupledIO(new TLBundleD(edge.bundle))
 }
 
-class FSMCSlvBase extends Module{
-  val io: FSMCSlvIO = IO(new FSMCSlvIO)
+abstract class FSMCMemBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{
+  val io: FSMCMemIO = IO(new FSMCMemIO)
 
-
-
-
-
-
-
-
-
-
-  mirror.io.datar_b,
-  mirror.io.ce_b,
-  mirror.io.we_b,
-  mirror.io.[10:0] addr_b,
-  mirror.io.[7:0] dataw_b
+  val sram = Module(new )
 }
 
-trait MirrorSRAM { this: FSMCSlvBase =>
+trait FSMCMemFSMC{ this: FSMCMemBase =>
 
 
 }
 
+trait FSMCMemTileLink { this: FSMCMemBase =>
 
+}
+
+class FSMCMem(edge: TLEdgeIn)(implicit p: Parameters) extends FSMCMemBase(edge)
+with FSMCMemFSMC
+with FSMCMemTileLink
+{
+
+}