Merge branch 'bug54' of github.com:whutddk/RISCV-MAC-SWICH into bug54

src/main/scala/backBoard/shin/SMUnit.scala

@@ -48,14 +48,14 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
   val isEmpty = ( wPtr === rPtr )
 
 
-  when( io.enq ){
+  when( io.enq & ~isFull ){
     wPtr := wPtr + 1.U
-    assert( ~isFull)
+    // assert( ~isFull)
   }
 
-  when( io.deq ){
+  when( io.deq & ~isEmpty ){
     rPtr := rPtr + 1.U
-    assert( ~isEmpty )
+    // assert( ~isEmpty )
   }
 
   for( i <- 0 until depth ){