CDR仿真文件

tb/shinTest/SimCDRTb.v

@@ -0,0 +1,96 @@
+`timescale 1 ns / 1 ps
+
+
+module SimCDRTb(
+
+);
+
+    reg clock = 0;
+    reg reset = 0;
+
+    reg [15:0] multiCLK;
+
+    initial begin
+        clock = 0;
+        reset = 1;
+
+        #100
+        reset <= 1;
+
+        #240
+        reset <= 0;
+    end
+
+
+    initial begin
+        forever begin #80 clock <= ~clock; end
+    end
+
+    generate
+    for( genvar i = 0; i < 16; i = i + 1 ) begin
+        initial begin
+        multiCLK[i] = 0;
+        for( integer j = 0; j < i; j = j + 1 ) begin
+            #20
+            ;
+        end
+        forever begin #80 multiCLK[i] <= ~multiCLK[i]; end
+        end
+    end  
+    endgenerate
+
+    reg [7:0] data;
+    wire success;
+    wire failed;
+
+    always @(posedge clock) begin
+        data <= $random;
+    end
+
+
+    SimCDR s_SimCDR(
+        .clock(clock),
+        .reset(reset),
+        .io_data(data),
+        .io_multiCLK_0(multiCLK[0]),
+        .io_multiCLK_1(multiCLK[1]),
+        .io_multiCLK_2(multiCLK[2]),
+        .io_multiCLK_3(multiCLK[3]),
+        .io_multiCLK_4(multiCLK[4]),
+        .io_multiCLK_5(multiCLK[5]),
+        .io_multiCLK_6(multiCLK[6]),
+        .io_multiCLK_7(multiCLK[7]),
+        .io_multiCLK_8(multiCLK[8]),
+        .io_multiCLK_9(multiCLK[9]),
+        .io_multiCLK_10(multiCLK[10]),
+        .io_multiCLK_11(multiCLK[11]),
+        .io_multiCLK_12(multiCLK[12]),
+        .io_multiCLK_13(multiCLK[13]),
+        .io_multiCLK_14(multiCLK[14]),
+        .io_multiCLK_15(multiCLK[15]),
+
+        .io_flush(1'b0),
+        .io_isSuccess(success),
+        .io_isFailed(failed)
+    );
+
+
+    initial
+    begin
+        $dumpfile("./tb/build/wave_cdr.vcd"); //生成的vcd文件名称
+        $dumpvars(0, SimCDRTb);//tb模块名称
+    end
+
+    always @(posedge clock) begin
+        if (success) begin
+            $display("Success onces! \n");
+        end
+        if (failed) begin
+            $display("Error! \n");
+            $stop;
+        end
+    end
+
+
+
+endmodule