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尝试加入cdr模块，主站上行rsp， tlast还有亚稳态

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This commit is contained in:
Ruige Lee
2025-05-06 17:39:52 +08:00
parent 9d53e4ea82
commit 19f4140dec
5 changed files with 197 additions and 267 deletions
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8
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -94,7 +94,7 @@ trait CDRInOverSample{ this: CDRInBase =>
trait CDRInAxis{ this: CDRInBase =>
def HeaderByte: Int = 8
def HeaderByte: Int = 4
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
@@ -107,7 +107,7 @@ trait CDRInAxis{ this: CDRInBase =>
val stateCurr = RegNext( stateNext, STATE_IDLE )
val bitCnt = Reg(UInt(4.W))
val byteCnt = RegInit(0.U(12.W))
val byteCnt = RegInit(0.U((12+1).W))
val syncSerDat: Bool
val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
@@ -125,8 +125,8 @@ trait CDRInAxis{ this: CDRInBase =>
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
))
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
)) //crc

70
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -5,19 +5,18 @@ import chisel3.util._
class ShinTopIO extends Bundle{
// val clk8x = Input(Bool())
// val modeSel = Input(Bool())
// val dDatIn = Input(Bool())
// val dDatOut = Output(Bool())
// val uDatIn = Input(Bool())
// val uDatOut = Output(Bool())
val clk8x = Input(Bool())
val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val downOut = Decoupled(new AXIS_Bundle(8))
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val upOut = Decoupled(new AXIS_Bundle(8))
// val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
// val downOut = Decoupled(new AXIS_Bundle(8))
// val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
// val upOut = Decoupled(new AXIS_Bundle(8))
// val qspi =
// val interrupt = Output(Bool())
@@ -59,6 +58,22 @@ abstract class ShinTopBase extends Module{
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
val downCDRIn = Module(new CDRIn)
val upCDRIn = Module(new CDRIn)
val downCDROut = Module(new CDROut)
val upCDROut = Module(new CDROut)
downCDRIn.io.serDat := io.dDatIn
downCDRIn.io.overCLK := io.clk8x
upCDRIn.io.serDat := io.uDatIn
upCDRIn.io.overCLK := io.clk8x
io.dDatOut := downCDROut.io.serDat
io.uDatOut := upCDROut.io.serDat
val smUnit = Seq(
Module( new SMUnit(depth = 4) ),
@@ -180,42 +195,36 @@ abstract class ShinTopBase extends Module{
smUnit(7).io.deq := false.B
io.downIn.ready := false.B
downCDRIn.io.axis.ready := false.B
slaveParser.io.downIn.valid := false.B
slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
slaveParser.io.downOut.ready := false.B
masterParser.io.downOut.ready := false.B
io.downOut.valid := false.B
io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
downCDROut.io.axis.valid := false.B
downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
io.upIn.ready := false.B
upCDRIn.io.axis.ready := false.B
slaveParser.io.upIn.valid := false.B
slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
masterParser.io.upIn.valid := false.B
masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
slaveParser.io.upOut.ready := false.B
io.upOut.valid := false.B
io.upOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
upCDROut.io.axis.valid := false.B
upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
}
}
trait ShinTopMaster{ this: ShinTopBase =>
when(io.modeSel === true.B ){
masterParser.io.downOut <> io.downOut
masterParser.io.upIn <> io.upIn
masterParser.io.downOut <> downCDROut.io.axis
masterParser.io.upIn <> upCDRIn.io.axis
}
when( io.modeSel === true.B ){
@@ -240,12 +249,11 @@ trait ShinTopMaster{ this: ShinTopBase =>
trait ShinTopSlave{ this: ShinTopBase =>
when( io.modeSel === false.B ){
slaveParser.io.downIn <> io.downIn
io.downOut <> slaveParser.io.downOut
slaveParser.io.upIn <> io.upIn
io.upOut <> slaveParser.io.upOut
slaveParser.io.downIn <> downCDRIn.io.axis
downCDROut.io.axis <> slaveParser.io.downOut
slaveParser.io.upIn <> upCDRIn.io.axis
upCDROut.io.axis <> slaveParser.io.upOut
}
slaveParser.io.timeStamp := io.timeStamp

51
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -57,17 +57,14 @@ abstract class SlaveParserBase extends Module{
val FRAME_STYLE_COMMON = 0.U
val FRAME_STYLE_PROBE = 1.U
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 3.U //子报文地址
val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 6.U //子报文数据
val STATE_CRC = 7.U //CRC校验
val STATE_ERROR = 8.U //
val STATE_WAIT = 9.U
val STATE_SUBMSG_HEADER = 2.U //子报文头
val STATE_PAYLOAD_DATA = 3.U //子报文数据
val STATE_CRC = 4.U //CRC校验
val STATE_ERROR = 5.U //
val STATE_WAIT = 6.U
@@ -463,7 +460,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val addrr = Reg(UInt(15.W))
val readSMAddr = Mux1H(Seq(
( upRecParser.io.stateCurr === STATE_PAYLOAD_WORKCNT ) -> upRecParser.io.subMsgReq.bits.address,
( upRecParser.io.stateCurr === STATE_SUBMSG_HEADER ) -> upRecParser.io.subMsgReq.bits.address,
( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA ) -> addrr,
))
@@ -631,14 +628,14 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
val isReadyToProbe_Pending = RegInit(false.B)
when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
isReadyToProbe := true.B
isReadyToProbe_Pending := true.B
} .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
isReadyToProbe := false.B
isReadyToProbe_Pending := false.B
} .elsewhen( isWatchDogOverflow ){
isReadyToProbe := false.B
isReadyToProbe_Pending := false.B
}
when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
@@ -649,16 +646,22 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
val isLastDevice_Pending = RegInit(true.B)
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
isLastDevice_Pending := false.B
} .elsewhen( isWatchDogOverflow ){
isLastDevice_Pending := true.B
}
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
probeRecCnt := 0.U
isLastDevice := false.B
} .elsewhen( isWatchDogOverflow ){
probeRecCnt := 0.U
isLastDevice := true.B
} .elsewhen( isReadyToProbe ){
probeRecCnt := probeRecCnt + 1.U
}
@@ -672,10 +675,14 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
io.upOut <> Queue( upSendGen.io.send, 1, true, true )
io.upOut <> Queue( upSendGen.io.send, 16, true, false )
io.downIn <> downRecParser.io.rec
val tmpFifo = Queue( downSendGen.io.send, 1, true, true )
val tmpFifo = Queue( downSendGen.io.send, 16, true, false )
when( isLastDevice & ~isReadyToProbe ){ //最后一个设备且不是探测模式
upRecParser.io.rec <> tmpFifo //axis短接
@@ -690,6 +697,14 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
io.upIn <> upRecParser.io.rec
}
when( isLastDevice =/= isLastDevice_Pending & ~downSendGen.io.send.valid & ~tmpFifo.valid & ~io.upIn.valid ){
isLastDevice := isLastDevice_Pending
}
when( isReadyToProbe =/= isReadyToProbe_Pending & ~downSendGen.io.send.valid & ~tmpFifo.valid & ~io.upIn.valid ){
isReadyToProbe := isReadyToProbe_Pending
}
}
class SlaveParser extends SlaveParserBase

174
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -28,14 +28,18 @@ class SlaveRecParser extends Module{
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 3.U //子报文地址
val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 6.U //子报文数据
val STATE_CRC = 7.U //CRC校验
val STATE_ERROR = 8.U //
val STATE_WAIT = 9.U
val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
// val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
// val STATE_PAYLOAD_ADDR = 3.U //子报文地址
// val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
// val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 3.U //子报文数据
val STATE_CRC = 4.U //CRC校验
val STATE_ERROR = 5.U //
val STATE_WAIT = 6.U
val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
@@ -46,10 +50,7 @@ class SlaveRecParser extends Module{
crc.io.isEnable :=
stateCurr === STATE_HEADER |
stateCurr === STATE_PAYLOAD_INDEX_STYLE |
stateCurr === STATE_PAYLOAD_ADDR |
stateCurr === STATE_PAYLOAD_OP_LENGTH |
stateCurr === STATE_PAYLOAD_WORKCNT |
stateCurr === STATE_SUBMSG_HEADER |
stateCurr === STATE_PAYLOAD_DATA
crc.io.dataIn := io.rec.bits.tdata
@@ -72,24 +73,17 @@ class SlaveRecParser extends Module{
val lengthCnt = Reg(UInt(11.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val lengthCnt = RegInit(0.U(12.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val isShortRx = ~io.rec.valid //接收长度小于预期
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext =/= STATE_HEADER)
io.frameReq.valid := io.rec.fire & (stateCurr === STATE_HEADER) & (stateNext =/= STATE_HEADER)
val frameHeader = Reg(new FrameHeader)
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
io.frameReq.bits.frameStyle := frameHeader.frameStyle
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
io.subMsgReq.valid := (stateCurr === STATE_PAYLOAD_WORKCNT) & (stateNext === STATE_PAYLOAD_DATA)
io.subMsgReq.valid := io.rec.fire & (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA)
val subMsgHeader = Reg(new SubMsgHeader)
io.subMsgReq.bits.devIndex := subMsgHeader.devIndex
@@ -100,102 +94,96 @@ class SlaveRecParser extends Module{
io.subMsgReq.bits.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
when( stateCurr === STATE_IDLE ){
lengthCnt := 0.U
} .elsewhen( stateCurr =/= stateNext ){
lengthCnt := 0.U
} .otherwise{
lengthCnt := lengthCnt + 1.U
when( io.rec.fire ){
when( stateCurr =/= stateNext ){
lengthCnt := 0.U
} .otherwise{
lengthCnt := lengthCnt + 1.U
}
}
when( stateCurr === STATE_IDLE || stateCurr === STATE_HEADER ){
frameLenCnt := 0.U
} .elsewhen(
( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) ||
( stateCurr === STATE_PAYLOAD_ADDR ) ||
( stateCurr === STATE_PAYLOAD_OP_LENGTH ) ||
( stateCurr === STATE_PAYLOAD_WORKCNT ) ||
( stateCurr === STATE_PAYLOAD_DATA )
){
frameLenCnt := frameLenCnt + 1.U
when( io.rec.fire ){
when( stateCurr === STATE_HEADER ){
frameLenCnt := 0.U
} .elsewhen(
( stateCurr === STATE_SUBMSG_HEADER ) ||
( stateCurr === STATE_PAYLOAD_DATA )
){
frameLenCnt := frameLenCnt + 1.U
}
}
io.data.valid := stateCurr === STATE_PAYLOAD_DATA
io.data.valid := io.rec.fire & stateCurr === STATE_PAYLOAD_DATA
io.data.bits := io.rec.bits.tdata
assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was rejected by fifo!" )
when( io.rec.fire ){
when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
frameHeader.frameLenAim := io.rec.bits.tdata << 4
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
frameHeader.frameStyle := io.rec.bits.tdata(1,0)
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 2.U ){
frameHeader.frameInfo := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 3.U ){
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
}
when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
frameHeader.frameLenAim := io.rec.bits.tdata << 4
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
frameHeader.frameStyle := io.rec.bits.tdata(1,0)
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 2.U ){
frameHeader.frameInfo := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 3.U ){
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
when( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 0.U ){
subMsgHeader.devIndex := io.rec.bits.tdata << 6
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 1.U ){
subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2)
subMsgHeader.style := io.rec.bits.tdata(1,0)
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 2.U ){
subMsgHeader.address := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 3.U ){
subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 4.U ){
subMsgHeader.operator := io.rec.bits.tdata(7,4)
subMsgHeader.length := io.rec.bits.tdata(3,0) << 8
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 5.U ){
subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 6.U ){
subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 7.U ){
subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
}
}
when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){
subMsgHeader.devIndex := io.rec.bits.tdata << 6
} .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){
subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2)
subMsgHeader.style := io.rec.bits.tdata(1,0)
}
when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){
subMsgHeader.address := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){
subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata
}
when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){
subMsgHeader.operator := io.rec.bits.tdata(7,4)
subMsgHeader.length := io.rec.bits.tdata(3,0) << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){
subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
}
when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){
subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){
subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
}
stateNext :=
Mux1H(Seq(
//必须使用上升沿触发，以避免前一帧长度超过预期
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt =/= (4-1).U, STATE_HEADER,
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (4-1).U,
MuxCase( STATE_ERROR, Array(
( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE,
( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_SUBMSG_HEADER,
( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC,
))
)
)), STATE_HEADER
)), STATE_HEADER
),
( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR )
),
( stateCurr === STATE_PAYLOAD_ADDR ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH )
),
( stateCurr === STATE_PAYLOAD_OP_LENGTH ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT )
),
( stateCurr === STATE_PAYLOAD_WORKCNT ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA )
),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( isShortRx, STATE_ERROR,
( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (8-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER )
), STATE_SUBMSG_HEADER),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === ( subMsgHeader.length - 1.U),
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
), STATE_PAYLOAD_DATA )
),
( stateCurr === STATE_CRC ) ->
Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), Mux( isShortRx, STATE_ERROR, STATE_CRC ) ),
), STATE_PAYLOAD_DATA),
( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast,
Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC
),
( stateCurr === STATE_ERROR ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ),
( stateCurr === STATE_WAIT ) -> Mux( io.resp, STATE_IDLE, STATE_WAIT )
))

161
tb/shinTest/ShinTopTb.v
View File

@@ -7,23 +7,12 @@ module ShinTopTb(
reg clock;
reg reset;
reg clk8x;
wire [3:0] dDat_w;
wire [3:0] uDat_w;
wire [3:0] io_down_ready;
wire [3:0] io_down_valid;
wire [31:0] io_down_bits_tdata;
wire [3:0] io_down_bits_tlast;
wire [3:0] io_down_bits_tuser;
wire [3:0] io_up_ready;
wire [3:0] io_up_valid;
wire [31:0] io_up_bits_tdata;
wire [3:0] io_up_bits_tlast;
wire [3:0] io_up_bits_tuser;
reg [63:0] timeStamp = 0;
@@ -41,26 +30,11 @@ ShinTop s_ShinTop_Mst(
.clock(clock),
.reset(reset),
.io_downIn_ready (),
.io_downIn_valid (1'b0),
.io_downIn_bits_tdata (8'd0),
.io_downIn_bits_tlast (1'b0),
.io_downIn_bits_tuser (1'b0),
.io_downOut_ready (io_down_ready[0]),
.io_downOut_valid (io_down_valid[0]),
.io_downOut_bits_tdata(io_down_bits_tdata[7:0]),
.io_downOut_bits_tlast(io_down_bits_tlast[0]),
.io_downOut_bits_tuser(io_down_bits_tuser[0]),
.io_upIn_ready (io_up_ready[0]),
.io_upIn_valid (io_up_valid[0]),
.io_upIn_bits_tdata (io_up_bits_tdata[7:0]),
.io_upIn_bits_tlast (io_up_bits_tlast[0]),
.io_upIn_bits_tuser (io_up_bits_tuser[0]),
.io_upOut_ready (1'b1),
.io_upOut_valid (),
.io_upOut_bits_tdata (),
.io_upOut_bits_tlast (),
.io_upOut_bits_tuser (),
.io_clk8x(clk8x),
.io_dDatIn(1'b0),
.io_dDatOut(dDat_w[0]),
.io_uDatIn(uDat_w[0]),
.io_uDatOut(),
.io_timeStamp(timeStamp),
@@ -114,26 +88,11 @@ ShinTop s_ShinTop_slv0(
.clock(clock),
.reset(reset),
.io_downIn_ready (io_down_ready[0]),
.io_downIn_valid (io_down_valid[0]),
.io_downIn_bits_tdata (io_down_bits_tdata[7:0]),
.io_downIn_bits_tlast (io_down_bits_tlast[0]),
.io_downIn_bits_tuser (io_down_bits_tuser[0]),
.io_downOut_ready (io_down_ready[1]),
.io_downOut_valid (io_down_valid[1]),
.io_downOut_bits_tdata(io_down_bits_tdata[15:8]),
.io_downOut_bits_tlast(io_down_bits_tlast[1]),
.io_downOut_bits_tuser(io_down_bits_tuser[1]),
.io_upIn_ready (io_up_ready[1]),
.io_upIn_valid (io_up_valid[1]),
.io_upIn_bits_tdata (io_up_bits_tdata[15:8]),
.io_upIn_bits_tlast (io_up_bits_tlast[1]),
.io_upIn_bits_tuser (io_up_bits_tuser[1]),
.io_upOut_ready (io_up_ready[0]),
.io_upOut_valid (io_up_valid[0]),
.io_upOut_bits_tdata (io_up_bits_tdata[7:0]),
.io_upOut_bits_tlast (io_up_bits_tlast[0]),
.io_upOut_bits_tuser (io_up_bits_tuser[0]),
.io_clk8x(clk8x),
.io_dDatIn(dDat_w[0]),
.io_dDatOut(dDat_w[1]),
.io_uDatIn(uDat_w[1]),
.io_uDatOut(uDat_w[0]),
.io_timeStamp(timeStamp),
@@ -186,26 +145,11 @@ ShinTop s_ShinTop_slv1(
.clock(clock),
.reset(reset),
.io_downIn_ready (io_down_ready[1]),
.io_downIn_valid (io_down_valid[1]),
.io_downIn_bits_tdata (io_down_bits_tdata[15:8]),
.io_downIn_bits_tlast (io_down_bits_tlast[1]),
.io_downIn_bits_tuser (io_down_bits_tuser[1]),
.io_downOut_ready (io_down_ready[2]),
.io_downOut_valid (io_down_valid[2]),
.io_downOut_bits_tdata(io_down_bits_tdata[23:16]),
.io_downOut_bits_tlast(io_down_bits_tlast[2]),
.io_downOut_bits_tuser(io_down_bits_tuser[2]),
.io_upIn_ready (io_up_ready[2]),
.io_upIn_valid (io_up_valid[2]),
.io_upIn_bits_tdata (io_up_bits_tdata[23:16]),
.io_upIn_bits_tlast (io_up_bits_tlast[2]),
.io_upIn_bits_tuser (io_up_bits_tuser[2]),
.io_upOut_ready (io_up_ready[1]),
.io_upOut_valid (io_up_valid[1]),
.io_upOut_bits_tdata (io_up_bits_tdata[15:8]),
.io_upOut_bits_tlast (io_up_bits_tlast[1]),
.io_upOut_bits_tuser (io_up_bits_tuser[1]),
.io_clk8x(clk8x),
.io_dDatIn(dDat_w[1]),
.io_dDatOut(dDat_w[2]),
.io_uDatIn(uDat_w[2]),
.io_uDatOut(uDat_w[1]),
.io_timeStamp(timeStamp),
@@ -258,26 +202,11 @@ ShinTop s_ShinTop_slv2(
.clock(clock),
.reset(reset),
.io_downIn_ready (io_down_ready[2]),
.io_downIn_valid (io_down_valid[2]),
.io_downIn_bits_tdata (io_down_bits_tdata[23:16]),
.io_downIn_bits_tlast (io_down_bits_tlast[2]),
.io_downIn_bits_tuser (io_down_bits_tuser[2]),
.io_downOut_ready (io_down_ready[3]),
.io_downOut_valid (io_down_valid[3]),
.io_downOut_bits_tdata(io_down_bits_tdata[31:24]),
.io_downOut_bits_tlast(io_down_bits_tlast[3]),
.io_downOut_bits_tuser(io_down_bits_tuser[3]),
.io_upIn_ready (io_up_ready[3]),
.io_upIn_valid (io_up_valid[3]),
.io_upIn_bits_tdata (io_up_bits_tdata[31:24]),
.io_upIn_bits_tlast (io_up_bits_tlast[3]),
.io_upIn_bits_tuser (io_up_bits_tuser[3]),
.io_upOut_ready (io_up_ready[2]),
.io_upOut_valid (io_up_valid[2]),
.io_upOut_bits_tdata (io_up_bits_tdata[23:16]),
.io_upOut_bits_tlast (io_up_bits_tlast[2]),
.io_upOut_bits_tuser (io_up_bits_tuser[2]),
.io_clk8x(clk8x),
.io_dDatIn(dDat_w[2]),
.io_dDatOut(dDat_w[3]),
.io_uDatIn(uDat_w[3]),
.io_uDatOut(uDat_w[2]),
.io_timeStamp(timeStamp),
@@ -330,26 +259,11 @@ ShinTop s_ShinTop_slv3(
.clock(clock),
.reset(reset),
.io_downIn_ready (io_down_ready[3]),
.io_downIn_valid (io_down_valid[3]),
.io_downIn_bits_tdata (io_down_bits_tdata[31:24]),
.io_downIn_bits_tlast (io_down_bits_tlast[3]),
.io_downIn_bits_tuser (io_down_bits_tuser[3]),
.io_downOut_ready (1'b1),
.io_downOut_valid (),
.io_downOut_bits_tdata(),
.io_downOut_bits_tlast(),
.io_downOut_bits_tuser(),
.io_upIn_ready (),
.io_upIn_valid (1'b0),
.io_upIn_bits_tdata (8'd0),
.io_upIn_bits_tlast (1'b0),
.io_upIn_bits_tuser (1'b0),
.io_upOut_ready (io_up_ready[3]),
.io_upOut_valid (io_up_valid[3]),
.io_upOut_bits_tdata (io_up_bits_tdata[31:24]),
.io_upOut_bits_tlast (io_up_bits_tlast[3]),
.io_upOut_bits_tuser (io_up_bits_tuser[3]),
.io_clk8x(clk8x),
.io_dDatIn(dDat_w[3]),
.io_dDatOut(),
.io_uDatIn(1'b0),
.io_uDatOut(uDat_w[3]),
.io_timeStamp(timeStamp),
@@ -412,21 +326,26 @@ end
initial begin
clock = 0;
clk8x = 0;
reset = 0;
#100
reset <= 1;
#100
#240
reset <= 0;
#1000000
#3000000
$display("Time Out !!!");
$stop;
end
initial begin
forever begin #10 clock <= ~clock; end
forever begin #10 clk8x <= ~clk8x; end
end
initial begin
forever begin #80 clock <= ~clock; end
end
initial
@@ -486,7 +405,7 @@ end
initial begin
//嗅探
#1000
#10000
begin
dataBuf[0] = 8'h00;
@@ -534,7 +453,7 @@ initial begin
// 顺序索引
#10000
#100000
begin
@@ -589,7 +508,7 @@ initial begin
//读写
#10000
#100000
begin
dataBuf[0] = 8'h20;
@@ -703,7 +622,7 @@ initial begin
// 同步
#20000
#200000
begin