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尝试加入cdr模块，主站上行rsp， tlast还有亚稳态

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This commit is contained in:
Ruige Lee
2025-05-06 17:39:52 +08:00
parent 9d53e4ea82
commit 19f4140dec
5 changed files with 197 additions and 267 deletions
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174
src/main/scala/backBoard/shin/SlaveRecParser.scala
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@@ -28,14 +28,18 @@ class SlaveRecParser extends Module{
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 3.U //子报文地址
val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 6.U //子报文数据
val STATE_CRC = 7.U //CRC校验
val STATE_ERROR = 8.U //
val STATE_WAIT = 9.U
val STATE_SUBMSG_HEADER = 2.U //子报文设备索引 //子报文类型
// val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
// val STATE_PAYLOAD_ADDR = 3.U //子报文地址
// val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
// val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 3.U //子报文数据
val STATE_CRC = 4.U //CRC校验
val STATE_ERROR = 5.U //
val STATE_WAIT = 6.U
val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
@@ -46,10 +50,7 @@ class SlaveRecParser extends Module{
crc.io.isEnable :=
stateCurr === STATE_HEADER |
stateCurr === STATE_PAYLOAD_INDEX_STYLE |
stateCurr === STATE_PAYLOAD_ADDR |
stateCurr === STATE_PAYLOAD_OP_LENGTH |
stateCurr === STATE_PAYLOAD_WORKCNT |
stateCurr === STATE_SUBMSG_HEADER |
stateCurr === STATE_PAYLOAD_DATA
crc.io.dataIn := io.rec.bits.tdata
@@ -72,24 +73,17 @@ class SlaveRecParser extends Module{
val lengthCnt = Reg(UInt(11.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val lengthCnt = RegInit(0.U(12.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val isShortRx = ~io.rec.valid //接收长度小于预期
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext =/= STATE_HEADER)
io.frameReq.valid := io.rec.fire & (stateCurr === STATE_HEADER) & (stateNext =/= STATE_HEADER)
val frameHeader = Reg(new FrameHeader)
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
io.frameReq.bits.frameStyle := frameHeader.frameStyle
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
io.subMsgReq.valid := (stateCurr === STATE_PAYLOAD_WORKCNT) & (stateNext === STATE_PAYLOAD_DATA)
io.subMsgReq.valid := io.rec.fire & (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA)
val subMsgHeader = Reg(new SubMsgHeader)
io.subMsgReq.bits.devIndex := subMsgHeader.devIndex
@@ -100,102 +94,96 @@ class SlaveRecParser extends Module{
io.subMsgReq.bits.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
when( stateCurr === STATE_IDLE ){
lengthCnt := 0.U
} .elsewhen( stateCurr =/= stateNext ){
lengthCnt := 0.U
} .otherwise{
lengthCnt := lengthCnt + 1.U
when( io.rec.fire ){
when( stateCurr =/= stateNext ){
lengthCnt := 0.U
} .otherwise{
lengthCnt := lengthCnt + 1.U
}
}
when( stateCurr === STATE_IDLE || stateCurr === STATE_HEADER ){
frameLenCnt := 0.U
} .elsewhen(
( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) ||
( stateCurr === STATE_PAYLOAD_ADDR ) ||
( stateCurr === STATE_PAYLOAD_OP_LENGTH ) ||
( stateCurr === STATE_PAYLOAD_WORKCNT ) ||
( stateCurr === STATE_PAYLOAD_DATA )
){
frameLenCnt := frameLenCnt + 1.U
when( io.rec.fire ){
when( stateCurr === STATE_HEADER ){
frameLenCnt := 0.U
} .elsewhen(
( stateCurr === STATE_SUBMSG_HEADER ) ||
( stateCurr === STATE_PAYLOAD_DATA )
){
frameLenCnt := frameLenCnt + 1.U
}
}
io.data.valid := stateCurr === STATE_PAYLOAD_DATA
io.data.valid := io.rec.fire & stateCurr === STATE_PAYLOAD_DATA
io.data.bits := io.rec.bits.tdata
assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was rejected by fifo!" )
when( io.rec.fire ){
when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
frameHeader.frameLenAim := io.rec.bits.tdata << 4
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
frameHeader.frameStyle := io.rec.bits.tdata(1,0)
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 2.U ){
frameHeader.frameInfo := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 3.U ){
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
}
when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
frameHeader.frameLenAim := io.rec.bits.tdata << 4
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 1.U ){
frameHeader.frameLenAim := frameHeader.frameLenAim | io.rec.bits.tdata(7,4)
frameHeader.frameStyle := io.rec.bits.tdata(1,0)
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 2.U ){
frameHeader.frameInfo := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_HEADER & lengthCnt === 3.U ){
frameHeader.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
when( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 0.U ){
subMsgHeader.devIndex := io.rec.bits.tdata << 6
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 1.U ){
subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2)
subMsgHeader.style := io.rec.bits.tdata(1,0)
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 2.U ){
subMsgHeader.address := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 3.U ){
subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 4.U ){
subMsgHeader.operator := io.rec.bits.tdata(7,4)
subMsgHeader.length := io.rec.bits.tdata(3,0) << 8
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 5.U ){
subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 6.U ){
subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8
} .elsewhen( stateCurr === STATE_SUBMSG_HEADER & lengthCnt === 7.U ){
subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
}
}
when( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 0.U ){
subMsgHeader.devIndex := io.rec.bits.tdata << 6
} .elsewhen( stateCurr === STATE_PAYLOAD_INDEX_STYLE & lengthCnt === 1.U ){
subMsgHeader.devIndex := subMsgHeader.devIndex | io.rec.bits.tdata(7,2)
subMsgHeader.style := io.rec.bits.tdata(1,0)
}
when( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 0.U ){
subMsgHeader.address := io.rec.bits.tdata << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_ADDR & lengthCnt === 1.U ){
subMsgHeader.address := subMsgHeader.address | io.rec.bits.tdata
}
when( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 0.U ){
subMsgHeader.operator := io.rec.bits.tdata(7,4)
subMsgHeader.length := io.rec.bits.tdata(3,0) << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_OP_LENGTH & lengthCnt === 1.U ){
subMsgHeader.length := subMsgHeader.length | io.rec.bits.tdata(7,0)
}
when( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 0.U ){
subMsgHeader.workCnt := io.rec.bits.tdata(7,0) << 8
} .elsewhen( stateCurr === STATE_PAYLOAD_WORKCNT & lengthCnt === 1.U ){
subMsgHeader.workCnt := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
}
stateNext :=
Mux1H(Seq(
//必须使用上升沿触发，以避免前一帧长度超过预期
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_HEADER ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt =/= (4-1).U, STATE_HEADER,
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (4-1).U,
MuxCase( STATE_ERROR, Array(
( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_PAYLOAD_INDEX_STYLE,
( frameHeader.frameStyle === FRAME_STYLE_COMMON ) -> STATE_SUBMSG_HEADER,
( frameHeader.frameStyle === FRAME_STYLE_PROBE ) -> STATE_CRC,
))
)
)), STATE_HEADER
)), STATE_HEADER
),
( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_INDEX_STYLE, STATE_PAYLOAD_ADDR )
),
( stateCurr === STATE_PAYLOAD_ADDR ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_ADDR, STATE_PAYLOAD_OP_LENGTH )
),
( stateCurr === STATE_PAYLOAD_OP_LENGTH ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_OP_LENGTH, STATE_PAYLOAD_WORKCNT )
),
( stateCurr === STATE_PAYLOAD_WORKCNT ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === 0.U, STATE_PAYLOAD_WORKCNT, STATE_PAYLOAD_DATA )
),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( isShortRx, STATE_ERROR,
( stateCurr === STATE_SUBMSG_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (8-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER )
), STATE_SUBMSG_HEADER),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === ( subMsgHeader.length - 1.U),
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
), STATE_PAYLOAD_DATA )
),
( stateCurr === STATE_CRC ) ->
Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), Mux( isShortRx, STATE_ERROR, STATE_CRC ) ),
), STATE_PAYLOAD_DATA),
( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast,
Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC
),
( stateCurr === STATE_ERROR ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ),
( stateCurr === STATE_WAIT ) -> Mux( io.resp, STATE_IDLE, STATE_WAIT )
))