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尝试加入cdr模块，主站上行rsp， tlast还有亚稳态

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This commit is contained in:
Ruige Lee
2025-05-06 17:39:52 +08:00
parent 9d53e4ea82
commit 19f4140dec
5 changed files with 197 additions and 267 deletions
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70
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -5,19 +5,18 @@ import chisel3.util._
class ShinTopIO extends Bundle{
// val clk8x = Input(Bool())
// val modeSel = Input(Bool())
// val dDatIn = Input(Bool())
// val dDatOut = Output(Bool())
// val uDatIn = Input(Bool())
// val uDatOut = Output(Bool())
val clk8x = Input(Bool())
val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val downOut = Decoupled(new AXIS_Bundle(8))
val dDatIn = Input(Bool())
val dDatOut = Output(Bool())
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
val upOut = Decoupled(new AXIS_Bundle(8))
// val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
// val downOut = Decoupled(new AXIS_Bundle(8))
// val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
// val upOut = Decoupled(new AXIS_Bundle(8))
// val qspi =
// val interrupt = Output(Bool())
@@ -59,6 +58,22 @@ abstract class ShinTopBase extends Module{
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
val downCDRIn = Module(new CDRIn)
val upCDRIn = Module(new CDRIn)
val downCDROut = Module(new CDROut)
val upCDROut = Module(new CDROut)
downCDRIn.io.serDat := io.dDatIn
downCDRIn.io.overCLK := io.clk8x
upCDRIn.io.serDat := io.uDatIn
upCDRIn.io.overCLK := io.clk8x
io.dDatOut := downCDROut.io.serDat
io.uDatOut := upCDROut.io.serDat
val smUnit = Seq(
Module( new SMUnit(depth = 4) ),
@@ -180,42 +195,36 @@ abstract class ShinTopBase extends Module{
smUnit(7).io.deq := false.B
io.downIn.ready := false.B
downCDRIn.io.axis.ready := false.B
slaveParser.io.downIn.valid := false.B
slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
slaveParser.io.downOut.ready := false.B
masterParser.io.downOut.ready := false.B
io.downOut.valid := false.B
io.downOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
downCDROut.io.axis.valid := false.B
downCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
io.upIn.ready := false.B
upCDRIn.io.axis.ready := false.B
slaveParser.io.upIn.valid := false.B
slaveParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
masterParser.io.upIn.valid := false.B
masterParser.io.upIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
slaveParser.io.upOut.ready := false.B
io.upOut.valid := false.B
io.upOut.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
upCDROut.io.axis.valid := false.B
upCDROut.io.axis.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
}
}
trait ShinTopMaster{ this: ShinTopBase =>
when(io.modeSel === true.B ){
masterParser.io.downOut <> io.downOut
masterParser.io.upIn <> io.upIn
masterParser.io.downOut <> downCDROut.io.axis
masterParser.io.upIn <> upCDRIn.io.axis
}
when( io.modeSel === true.B ){
@@ -240,12 +249,11 @@ trait ShinTopMaster{ this: ShinTopBase =>
trait ShinTopSlave{ this: ShinTopBase =>
when( io.modeSel === false.B ){
slaveParser.io.downIn <> io.downIn
io.downOut <> slaveParser.io.downOut
slaveParser.io.upIn <> io.upIn
io.upOut <> slaveParser.io.upOut
slaveParser.io.downIn <> downCDRIn.io.axis
downCDROut.io.axis <> slaveParser.io.downOut
slaveParser.io.upIn <> upCDRIn.io.axis
upCDROut.io.axis <> slaveParser.io.upOut
}
slaveParser.io.timeStamp := io.timeStamp