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尝试加入cdr模块，主站上行rsp， tlast还有亚稳态

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This commit is contained in:
Ruige Lee
2025-05-06 17:39:52 +08:00
parent 9d53e4ea82
commit 19f4140dec
5 changed files with 197 additions and 267 deletions
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8
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -94,7 +94,7 @@ trait CDRInOverSample{ this: CDRInBase =>
trait CDRInAxis{ this: CDRInBase =>
def HeaderByte: Int = 8
def HeaderByte: Int = 4
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
@@ -107,7 +107,7 @@ trait CDRInAxis{ this: CDRInBase =>
val stateCurr = RegNext( stateNext, STATE_IDLE )
val bitCnt = Reg(UInt(4.W))
val byteCnt = RegInit(0.U(12.W))
val byteCnt = RegInit(0.U((12+1).W))
val syncSerDat: Bool
val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
@@ -125,8 +125,8 @@ trait CDRInAxis{ this: CDRInBase =>
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
))
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
)) //crc