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增加生成从站造SM数据的python代码,生成verilog测试代码;修改相关的测试用例;修改打印的输出信息

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bacon
2025-06-26 16:37:12 +08:00
parent 672cc519bb
commit 18170d00da
2 changed files with 83 additions and 45 deletions
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74
tb/shinTest/ShinTopSpiTb.v
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@@ -9,7 +9,7 @@
`define ENABLE_EXCHG_DATA_SEQ0_TEST
//`define ENABLE_EXCHG_DATA_SEQ1_TEST
//`define ENABLE_EXCHG_DATA_SEQ2_TEST
`define ENABLE_EXCHG_DATA_SEQ2_TEST
//`define ENABLE_EXCHG_DATA_SEQ3_TEST
//`define ENABLE_BC_R_TEST
@@ -17,9 +17,9 @@
//`define ENABLE_BC_RW_TEST
`define ENABLE_SYNC_TEST
`define ENABLE_SYNC_SIG0_TEST
`define ENABLE_SYNC_SIG1_TEST
`define ENABLE_RESET_TEST
//`define ENABLE_SYNC_SIG0_TEST
//`define ENABLE_SYNC_SIG1_TEST
//`define ENABLE_RESET_TEST
//`define ENABLE_EBMMU_TC1_TEST
//`define ENABLE_EBMMU_TC2_TEST
@@ -457,6 +457,35 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
_len = rxBuf[_pos + 5] + (rxBuf[_pos + 4] & 8'h0f) * 256;
end
end
begin:PRINT_PKT_COMMENT
integer dev;
integer addr_type;
integer addr;
integer cmd;
integer len;
if (scmd == 0) begin
addr_type = txBuf[_pos + 1] & 8'h3;
dev = txBuf[_pos] * 256 + ((txBuf[_pos + 1] >> 2) & 8'hff);
addr = txBuf[_pos + 2] * 256 + (txBuf[_pos + 3] & 8'hff);
cmd = (txBuf[_pos + 4] >> 4) & 8'h0f;
len = (txBuf[_pos + 4] & 8'h0f) * 256 + (txBuf[_pos + 5] & 8'hff);
end else begin
addr_type = rxBuf[_pos + 1] & 8'h3;
dev = rxBuf[_pos] * 256 + ((rxBuf[_pos + 1] >> 2) & 8'hff);
addr = rxBuf[_pos + 2] * 256 + (rxBuf[_pos + 3] & 8'hff);
cmd = (rxBuf[_pos + 4] >> 4) & 8'h0f;
len = (rxBuf[_pos + 4] & 8'h0f) * 256 + (rxBuf[_pos + 5] & 8'hff);
end
if (addr_type == 0)
$fwrite(spidata_file, "// type:%3d dev:%3d addr:0x%04x cmd:0x%1x len:%3d", addr_type, dev, addr[15:0], cmd[3:0], len);
else begin
addr = dev * 65536 + addr;
$fwrite(spidata_file, "// type:%3d addr:0x08x cmd:0x%1x len:%3d", addr_type, addr, cmd[3:0], len);
end
end
$fwrite(spidata_file, "\n{{ ");
_pos = _pos + 6;
@@ -991,43 +1020,6 @@ initial begin
$fdisplay(spidata_file, "\n\n测试用例：交换数据读dev1_sm1/dev2_sm3/dev3_sm5/dev4_sm7");
$display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp);
txBuf[3] = 8'h80;
txBuf[4] = 8'h00;
spi_trans((16'h0306), (`SPI_WRITE), (2), (`IF_IDX(1)) );//dev1_sm1
txBuf[3] = 8'h98;
txBuf[4] = 8'h00;
spi_trans((16'h030e), (`SPI_WRITE), (2), (`IF_IDX(2)) );//dev2_sm3
txBuf[3] = 8'h81;
txBuf[4] = 8'h00;
spi_trans((16'h0316), (`SPI_WRITE), (2), (`IF_IDX(3)) );//dev2_sm3
txBuf[3] = 8'h8c;
txBuf[4] = 8'h00;
spi_trans((16'h031e), (`SPI_WRITE), (2), (`IF_IDX(4)) );//dev2_sm3
for (integer i=0; i < 128; i++) begin
txBuf[i + 3] = i + 1;
end
spi_trans( (16'h1000), (`SPI_WRITE), (128), (`IF_IDX(1)) );
for (integer i=0; i < 152; i++) begin
txBuf[i + 3] = i + 2;
end
spi_trans( (16'h2000), (`SPI_WRITE), (152), (`IF_IDX(2)) );
for (integer i=0; i < 129; i++) begin
txBuf[i + 3] = i + 3;
end
spi_trans( (16'h3000), (`SPI_WRITE), (129), (`IF_IDX(3)) );
for (integer i=0; i < 140; i++) begin
txBuf[i + 3] = i + 4;
end
spi_trans( (16'h4000), (`SPI_WRITE), (140), (`IF_IDX(4)) );
`include "seq_2_pkt.vh"
_t_end = $realtime;