增加cdr的配置选项，可以让cdr正常工作

2025-09-22 17:52:12 +08:00
parent e8f3ee8dcf
commit 1716ae1e04
7 changed files with 44 additions and 14 deletions
--- a/5
+++ b/5
@@ -10,6 +10,7 @@ SPI_TYPE ?= -spi 0
 TRANS_CODE ?= 
 DEVCLK ?= --dev1 0 90 --dev2 0 -90
 CDRCLK ?= --clk 0 40
+CDR_TYPE ?= -cdr 0

 ifeq "$(RVCCVERSION)" "12.2.0"
   	ISR_MARCH=-march=rv32izicsr -mabi=ilp32
@@ -24,7 +25,7 @@ shin:
 	sbt "test:runMain test.testShinModule"

 testShin:
-	python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
+	python3 ./tb/shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	iverilog -Wall  \
@@ -38,7 +39,7 @@ testShin:
 	python3 ./tb/shinTest/check_testcase.py

 testShinClk:
-	python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE}
+	python3 ./tb/shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	iverilog -Wall  \
--- a/tb/shinTest/Makefile_vcs
+++ b/tb/shinTest/Makefile_vcs
@@ -4,7 +4,8 @@ OUTPUT = shin_test
 CPU_COUNT := $(shell nproc)
 SPI_TYPE ?= -spi 0
 TRANS_CODE ?= 
-DEVCLK ?= --dev1 0 90 --dev2 0 -90
+DEVCLK ?= --dev1 0 90 --dev2 0 -88
+CDR_TYPE ?= -cdr 0

 VCS = vcs -sverilog +v2k -timescale=1ns/1ps   \
 	-full64                                   \
@@ -21,16 +22,16 @@ testShin_vcs:
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	@echo "Available CPUs: ${CPU_COUNT}"
-	${VCS} -f ./shinTest_vcs.f
+	${VCS} -f ./shinTest_vcs.f 1>vcs_compile.log 2>&1
 	${SIM}
 	python3 ./shinTest/check_testcase.py

 testShinClk_vcs:
-	python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE}
+	python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
-	${VCS} -f ./shinTestClk_vcs.f
-	${SIM}
+	${VCS} -f ./shinTestClk_vcs.f 1>vcs_compile.log 2>&1
+	${SIM} 
 	python3 ./shinTest/check_testcase.py


@@ -47,7 +48,7 @@ sim:
 	${SIM}

 testShin:
-	./shinTest/gen_pkt.py
+	./shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	iverilog -Wall  \
@@ -60,7 +61,7 @@ testShin:
 	./shinTest/check_testcase.py

 testShinClk:
-	./shinTest/gen_pkt_clk.py --dev1 0 200
+	./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	iverilog -Wall  \
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -119,6 +119,11 @@ ShinTop s_ShinTop_Mst(
  .io_multiCLK_14(multiCLK[14]),
  .io_multiCLK_15(multiCLK[15]),

+  .io_multiCLKDiv4_0(multiCLK[0]),
+  .io_multiCLKDiv4_1(multiCLK[4]),
+  .io_multiCLKDiv4_2(multiCLK[8]),
+  .io_multiCLKDiv4_3(multiCLK[12]),
+
  .io_dDatIn(1'b0),
  .io_dDatOut(dDat_w[0]),
  .io_uDatIn(uDat_w[0]),
--- a/tb/shinTest/ShinTopSpiTb_clk.v
+++ b/tb/shinTest/ShinTopSpiTb_clk.v
@@ -111,6 +111,11 @@ ShinTop s_ShinTop_Mst(
  .io_multiCLK_14(multiCLK[14]),
  .io_multiCLK_15(multiCLK[15]),

+  .io_multiCLKDiv4_0(multiCLK[0]),
+  .io_multiCLKDiv4_1(multiCLK[4]),
+  .io_multiCLKDiv4_2(multiCLK[8]),
+  .io_multiCLKDiv4_3(multiCLK[12]),
+
  .io_dDatIn(1'b0),
  .io_dDatOut(dDat_w[0]),
  .io_uDatIn(uDat_w[0]),
@@ -480,11 +485,14 @@ begin
  	if (!spidata_file) $display("文件打开失败");
    `ifdef VCS_COMPILE
    $dumpfile("./generated/wave.vcd"); //生成的vcd文件名称
-	$dumpvars(0, ShinTopSpiTb);//tb模块名称
+	//$dumpvars(0, ShinTopSpiTb);//tb模块名称
+    $dumpvars(0, ShinTopSpiTb.s_ShinTop_Mst);
+    $dumpvars(0, ShinTopSpiTb.s_ShinTop_slv0);
+    //$dumpvars(0, ShinTopSpiTb.s_ShinTop_slv1);
    `endif

    `ifdef IVERILOG_COMPILE
-	$dumpfile("./generated/wave.fst"); //生成的fst文件名称
+	$dumpfile("./generated/wave_clk.fst"); //生成的fst文件名称
 	$dumpvars(0, ShinTopSpiTb);//tb模块名称
    `endif
 end
--- a/tb/shinTest/gen_pkt.py
+++ b/tb/shinTest/gen_pkt.py
@@ -11,6 +11,7 @@ if __name__ == '__main__':
    # 可选参数
    parser.add_argument("-8b10b", action="store_true", dest="use_8b10b", default=False, help="使用8b10b编码")
    parser.add_argument("-spi", dest="spi_type", type=int, default=0, help="选择SPI，0:ISPI;1:OSPI;2:OQSPI;3:AQSPI")
+    parser.add_argument("-cdr", dest="cdr_type", type=int, default=0, help="选择CDR")
    # 解析参数
    args = parser.parse_args()
    
@@ -19,6 +20,7 @@ if __name__ == '__main__':
    #print(args.spi_type)
    environment.set_spi_interface(args.spi_type)
    environment.set_using_8b10b(args.use_8b10b)
+    environment.set_cdr_type(args.cdr_type)
    
    environment.gen_slv_dev_num(4)
    environment.bringup()
--- a/tb/shinTest/gen_pkt_clk.py
+++ b/tb/shinTest/gen_pkt_clk.py
@@ -15,6 +15,7 @@ if __name__ == '__main__':
    parser.add_argument("-d4", "--dev4",  nargs=2, type=int, default=[0, 0], help="相位(度)、频率偏差ppm")
    parser.add_argument("-8b10b", action="store_true", dest="use_8b10b", default=False, help="使用8b10b编码")
    parser.add_argument("-spi", dest="spi_type", type=int, default=0, help="选择SPI，0:ISPI;1:OSPI;2:OQSPI;3:AQSPI")
+    parser.add_argument("-cdr", dest="cdr_type", type=int, default=0, help="选择CDR")

    # 解析参数
    args = parser.parse_args()    
@@ -35,6 +36,7 @@ if __name__ == '__main__':
    environment.set_dev_clk(dev_clk_info)
    environment.set_spi_interface(args.spi_type)
    environment.set_using_8b10b(args.use_8b10b)
+    environment.set_cdr_type(args.cdr_type)

    environment.gen_slv_dev_for_clk(4)
    
--- a/tb/shinTest/testcase/environment.py
+++ b/tb/shinTest/testcase/environment.py
@@ -5,6 +5,7 @@ global_dev_num = 4
 global_setting_dev_clk = dict()
 global_using_8b10b = False
 global_spi_type = 0
+global_cdr_type = 0

 def bringup():
    gen_file_def = "sys_bringup"
@@ -226,6 +227,11 @@ def __GenDevice(id, TerminateNode = False):
        +"\t.io_multiCLK_14(%s[14]),\n"%(multiclk, )
        +"\t.io_multiCLK_15(%s[15]),\n\n"%(multiclk, )

+        +"\t.io_multiCLKDiv4_0(%s[0]),\n"%(multiclk, )
+        +"\t.io_multiCLKDiv4_1(%s[4]),\n"%(multiclk, )
+        +"\t.io_multiCLKDiv4_2(%s[8]),\n"%(multiclk, )
+        +"\t.io_multiCLKDiv4_3(%s[12]),\n\n"%(multiclk, )
+
        +"\t.io_dDatIn(dDat_w[%d]),\n"%(id, )
        +"\t.io_dDatOut(%s),\n"%(dout_code, )
        +"\t.io_uDatIn(%s),\n"%(din_code, )
@@ -450,15 +456,20 @@ def set_using_8b10b(isUsing8b10b):
    global global_using_8b10b
    global_using_8b10b = isUsing8b10b
    
+def set_cdr_type(cdr_type):
+    global global_cdr_type
+    global_cdr_type = cdr_type
+    
 def using_proper_workmode(dev, iface=1):
    global global_using_8b10b
    global global_spi_type
+    global global_cdr_type
    
    trans_code = 0x0
    
    if global_using_8b10b:
        trans_code = 0x1
    
-    return genIFRwDataCode(dev, 0x09, True, 1, [global_spi_type, ], wlog=False, iface=iface)+genIFRwDataCode(dev, 0x004c, True, 2, [trans_code, 0x59], wlog = False)
-    
-    
+    return genIFRwDataCode(dev, 0x09, True, 1, [global_spi_type, ], wlog=False, iface=iface)\
+        +genIFRwDataCode(dev, 0x004c, True, 2, [trans_code, 0x59], wlog = False)\
+        +genIFRwDataCode(dev, 0x004e, True, 2, [global_cdr_type, 0x60], wlog = False)