增加cdr的配置选项，可以让cdr正常工作

tb/shinTest/Makefile_vcs

@@ -4,7 +4,8 @@ OUTPUT = shin_test
 CPU_COUNT := $(shell nproc)
 SPI_TYPE ?= -spi 0
 TRANS_CODE ?= 
-DEVCLK ?= --dev1 0 90 --dev2 0 -90
+DEVCLK ?= --dev1 0 90 --dev2 0 -88
+CDR_TYPE ?= -cdr 0
 
 VCS = vcs -sverilog +v2k -timescale=1ns/1ps   \
 	-full64                                   \
@@ -21,16 +22,16 @@ testShin_vcs:
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	@echo "Available CPUs: ${CPU_COUNT}"
-	${VCS} -f ./shinTest_vcs.f
+	${VCS} -f ./shinTest_vcs.f 1>vcs_compile.log 2>&1
 	${SIM}
 	python3 ./shinTest/check_testcase.py
 
 testShinClk_vcs:
-	python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE}
+	python3 ./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
-	${VCS} -f ./shinTestClk_vcs.f
-	${SIM}
+	${VCS} -f ./shinTestClk_vcs.f 1>vcs_compile.log 2>&1
+	${SIM} 
 	python3 ./shinTest/check_testcase.py
 
 
@@ -47,7 +48,7 @@ sim:
 	${SIM}
 
 testShin:
-	./shinTest/gen_pkt.py
+	./shinTest/gen_pkt.py ${SPI_TYPE} ${TRANS_CODE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	iverilog -Wall  \
@@ -60,7 +61,7 @@ testShin:
 	./shinTest/check_testcase.py
 
 testShinClk:
-	./shinTest/gen_pkt_clk.py --dev1 0 200
+	./shinTest/gen_pkt_clk.py ${DEVCLK} ${SPI_TYPE} ${TRANS_CODE} ${CDR_TYPE}
 	mkdir -p generated/log
 	rm -rf generated/log/*
 	iverilog -Wall  \