diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala
index aeed6f6..a62caca 100644
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -49,6 +49,8 @@ class CDROut extends Module{
       (stateCurr === STATE_PAYLOAD)
     )
 
+  assert( ~(~io.axis.valid & io.axis.ready) )
+
 
 
   when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 4f9b865..3c835cb 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -38,10 +38,12 @@ class CommonRegisterBundle extends Bundle{
   val syncPoint = UInt(64.W)
   val syncPeroid = UInt(32.W)
 
+  val custom = Vec( 128, UInt(8.W) )
 
-  val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
-  val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
 
+  // val smEnqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
+  // val smDeqAddr = Vec(8, UInt(11.W)) //触发SM切换缓冲区的地址 （或读或写）
+  val smTrigLen = Vec(8, UInt(11.W))  //触发SM切换缓冲区的地址 （或读或写）
 
 
 }
@@ -51,7 +53,7 @@ class MasterRegisterBundle extends Bundle{
 
   val txSM         = UInt(2.W)
   val rxSM         = UInt(2.W)
-  val txLength     = UInt(12.W)
+  // val txLength     = UInt(12.W)
   // val txStatus     = UInt(16.W)
 
   val rplTimeStampTx = UInt(16.W)
@@ -156,7 +158,7 @@ class InterfaceIO extends Bundle{
   val txReq = Valid(new Bundle{
     val txSM = UInt(2.W)
     val rxSM = UInt(2.W)
-    val txLength = UInt(12.W)
+    // val txLength = UInt(12.W)
   }) //发送请求和SM代号
 
 
@@ -182,9 +184,6 @@ class InterfaceIO extends Bundle{
 
 
 
-  // val smEnqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
-  // val smDeqAddr = Output(Vec(8, UInt(16.W))) //触发SM切换缓冲区的地址 （或读或写）
-  // val mstTimeStamp  = Input(UInt(64.W)) //主站时间戳
   val slvDeltaTime  = Input(UInt(32.W)) //从站时间戳差值
   val mstDeltaTime  = Input(UInt(32.W))
   val deltaFinal = Input(UInt(32.W))
@@ -249,7 +248,7 @@ abstract class InterfaceBase extends Module{
 
 
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
-                (addr === "h21".U & isMstMode) -> mReg.txLength,
+                //(addr === "h21".U & isMstMode) -> mReg.txLength,
 
         (addr === "h24".U & isMstMode) -> mReg.rplTimeStampTx(7,0),
         (addr === "h25".U & isMstMode) -> mReg.rplTimeStampTx(15,8),
@@ -357,9 +356,20 @@ abstract class InterfaceBase extends Module{
         (addr === "h145".U & isSlvMode)  -> sReg.syncOffset(3)(15,8),
         (addr === "h146".U & isSlvMode)  -> sReg.syncOffset(3)(23,16),
         (addr === "h147".U & isSlvMode)  -> sReg.syncOffset(3)(31,24),
-      )
-
+      ) ++
+      ( 0 until 128 ).map{ i =>
+        ( addr === ("h180".U + i.U )   ) -> cReg.custom(i)
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h302".U + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
+      } ++
+      ( 0 until 8 ).map{ i =>
+        ( addr === ("h303".U + (i*4).U) )  -> cReg.smTrigLen(i)(10,8)
+      } ++
+      Seq()
     )
+
+
   }
 
 
@@ -455,7 +465,14 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U )
-  mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
+  // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) )
+
+  ( 0 until 128 ).map{ i =>
+    cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrSel === ("h180".U + i.U)) )
+  }
+
+
+
 
   mReg.rplTimeStampTx := 
     Cat(
@@ -529,16 +546,12 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
   val isEnR: Bool
 
   for( i <- 0 until 8 ){
-    cReg.smEnqAddr(i) := 
+    cReg.smTrigLen(i) := 
       Cat(
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h201".U + (i*2).U) ),
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h200".U + (i*2).U) ),
-      )
-    cReg.smDeqAddr(i) := 
-      Cat(
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h301".U + (i*2).U) ),
-        RegEnable( dataw, 0.U, isEnW & addrSel === ("h300".U + (i*2).U) ),
+        RegEnable( dataw, 0.U, isEnW & addrSel === ("h303".U + (i*4).U) ),
+        RegEnable( dataw, 0.U, isEnW & addrSel === ("h302".U + (i*4).U) ),
       )
+
   }
 
 
@@ -567,15 +580,15 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
   io.sram_w(2).enw   := isEnW & (( addrSel & "hF800".U ) === "h3000".U)
   io.sram_w(3).enw   := isEnW & (( addrSel & "hF800".U ) === "h4000".U)
 
-  io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(0))
-  io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(2))
-  io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(4))
-  io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smDeqAddr(6))
+  io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(0) - 1.U)
+  io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(2) - 1.U)
+  io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(4) - 1.U)
+  io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(6) - 1.U)
 
-  io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smEnqAddr(1))
-  io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smEnqAddr(3))
-  io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smEnqAddr(5))
-  io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smEnqAddr(7))
+  io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smTrigLen(1) - 1.U)
+  io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smTrigLen(3) - 1.U)
+  io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smTrigLen(5) - 1.U)
+  io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smTrigLen(7) - 1.U)
 }
 
 trait InterfaceLVDSop{ this: InterfaceBase =>
@@ -723,11 +736,10 @@ with InterfaceSync
 
   io.txReq.bits.txSM  := mReg.txSM
   io.txReq.bits.rxSM  := mReg.rxSM
-  io.txReq.bits.txLength := mReg.txLength
+  // io.txReq.bits.txLength := //mReg.txLength
   io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U
 
-  // io.smEnqAddr := cReg.smEnqAddr
-  // io.smDeqAddr := cReg.smDeqAddr
+
 
 
   sReg.localDevIndex := io.localDevIndex
diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala
index 9c5fc0e..6f4fe88 100644
--- a/src/main/scala/backBoard/shin/MasterParser.scala
+++ b/src/main/scala/backBoard/shin/MasterParser.scala
@@ -10,12 +10,9 @@ class MasterParserIO extends Bundle{
   val sram_w = Flipped(new SRAM2kWRIO)
   val sram_r = Flipped(new SRAM2kRDIO)
 
-  val req = Flipped(Valid(new Bundle{
-    val txLength  = UInt(12.W)
-  }))
+  val req = Input(Bool())
   val rsp = Valid(new Bundle{
     val isError = Bool()
-    val length  = UInt(12.W)
   })
 
   val rxEnq = Output( Bool())
@@ -50,27 +47,37 @@ abstract class MasterParserBase extends Module{
 
   // io.req.ready := reqReady
 
-  when( io.req.fire ){
+  when( io.req ){
     reqReady := false.B
   } .elsewhen( io.downOut.fire & txCnt === txLen + (4-1).U ){
     reqReady := true.B
   }
 
-  when( io.req.fire ){
-    txLen  := io.req.bits.txLength
-    rxLen  := io.req.bits.txLength
+  when( io.req ){
+    txLen := Mux1H(Seq(
+      ( io.mReg.txSM === 0.U ) -> io.cReg.smTrigLen(1),
+      ( io.mReg.txSM === 1.U ) -> io.cReg.smTrigLen(3),
+      ( io.mReg.txSM === 2.U ) -> io.cReg.smTrigLen(5),
+      ( io.mReg.txSM === 3.U ) -> io.cReg.smTrigLen(7),
+    ))
+    rxLen := Mux1H(Seq(
+      ( io.mReg.rxSM === 0.U ) -> io.cReg.smTrigLen(0),
+      ( io.mReg.rxSM === 1.U ) -> io.cReg.smTrigLen(2),
+      ( io.mReg.rxSM === 2.U ) -> io.cReg.smTrigLen(4),
+      ( io.mReg.rxSM === 3.U ) -> io.cReg.smTrigLen(6),
+    ))
     txCnt  := 0.U
   } .elsewhen( io.downOut.fire ){
     txCnt := txCnt + 1.U
   }
 
-  when( io.req.fire ){
+  when( io.req ){
     txAddr := 0.U
   } .elsewhen( io.downOut.fire ){
     txAddr := txAddr + 1.U
   }
 
-  when( io.req.fire ){
+  when( io.req ){
     rxAddr := 0.U
   } .elsewhen( io.upIn.fire ){
     rxAddr := rxAddr + 1.U
@@ -79,9 +86,9 @@ abstract class MasterParserBase extends Module{
 
 
   io.sram_r.enr := 
-    io.req.fire | io.downOut.fire
+    io.req | io.downOut.fire
 
-  io.sram_r.addrr := Mux( io.req.fire, 0.U, txAddr + 1.U )
+  io.sram_r.addrr := Mux( io.req, 0.U, txAddr + 1.U )
 
   io.downOut.valid := ~reqReady
 
@@ -130,7 +137,7 @@ abstract class MasterParserBase extends Module{
 
   val recCrcCheck = Reg(UInt(32.W))
 
-  when( io.req.fire ){
+  when( io.req ){
     rxCnt := 0.U
   } .elsewhen( io.upIn.fire ){
     rxCnt := rxCnt + 1.U
@@ -146,12 +153,12 @@ abstract class MasterParserBase extends Module{
 
   io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
   io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tlast & recCrcCheck =/= rxcrc.io.crc
-  io.rsp.bits.length  := rxCnt + 1.U
+  // io.rsp.bits.length  := rxCnt + 1.U
 
 
 
-  io.rxEnq := io.downOut.fire & io.downOut.bits.tlast
-  io.txDeq := io.upIn.fire    & io.upIn.bits.tlast
+  io.rxEnq := io.upIn.fire    & io.upIn.bits.tlast
+  io.txDeq := io.downOut.fire & io.downOut.bits.tlast
 
 
 
diff --git a/src/main/scala/backBoard/shin/SMUnit.scala b/src/main/scala/backBoard/shin/SMUnit.scala
index b0a407e..befeb8e 100644
--- a/src/main/scala/backBoard/shin/SMUnit.scala
+++ b/src/main/scala/backBoard/shin/SMUnit.scala
@@ -50,10 +50,12 @@ abstract class SMUnitBase(depth: Int = 4) extends Module {
 
   when( io.enq ){
     wPtr := wPtr + 1.U
+    assert( ~isFull)
   }
 
   when( io.deq ){
     rPtr := rPtr + 1.U
+    assert( ~isEmpty )
   }
 
   for( i <- 0 until depth ){
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 317ff0f..fd75bb4 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -38,7 +38,7 @@ class ShinTopIO extends Bundle{
 
   val rsp = Valid(new Bundle{
     val isError = Bool()
-    val length  = UInt(12.W)
+    // val length  = UInt(12.W)
   })
 
   val iSync = Output(Vec(4, Bool()))
@@ -268,21 +268,13 @@ trait ShinTopMaster{ this: ShinTopBase =>
       smUnit(7).io.deq    := masterParser.io.txDeq
     }
 
-    // _ := interface.io.smEnqAddr(0)
-    // _ := interface.io.smDeqAddr(1)
-    // _ := interface.io.smEnqAddr(2)
-    // _ := interface.io.smDeqAddr(3)
-    // _ := interface.io.smEnqAddr(4)
-    // _ := interface.io.smDeqAddr(5)
-    // _ := interface.io.smEnqAddr(6)
-    // _ := interface.io.smDeqAddr(7)
 
 
     interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp
   }
 
-  masterParser.io.req.valid         := interface.io.txReq.valid
-  masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
+  masterParser.io.req         := interface.io.txReq.valid
+  // masterParser.io.req.bits.txLength := interface.io.txReq.bits.txLength
 
   io.rsp := masterParser.io.rsp
 
@@ -305,20 +297,6 @@ trait ShinTopSlave{ this: ShinTopBase =>
   slaveParser.io.cReg := interface.io.cReg
 
 
-
-  slaveParser.io.trigAddr(0) := interface.io.cReg.smEnqAddr(0)
-  slaveParser.io.trigAddr(1) := interface.io.cReg.smDeqAddr(1)
-  slaveParser.io.trigAddr(2) := interface.io.cReg.smEnqAddr(2)
-  slaveParser.io.trigAddr(3) := interface.io.cReg.smDeqAddr(3)
-  slaveParser.io.trigAddr(4) := interface.io.cReg.smEnqAddr(4)
-  slaveParser.io.trigAddr(5) := interface.io.cReg.smDeqAddr(5)
-  slaveParser.io.trigAddr(6) := interface.io.cReg.smEnqAddr(6)
-  slaveParser.io.trigAddr(7) := interface.io.cReg.smDeqAddr(7)
-
-
-
-
-
   when( interface.io.cReg.modeSel === false.B ){
     smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
     smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 73d0653..4b72c40 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -44,7 +44,7 @@ class SlaveParserIO extends Bundle{
   val dSMenq = Output( Vec(4, Bool()) )
   val uSMdeq = Output( Vec(4, Bool()) )
 
-  val trigAddr = Input( Vec(8, UInt(15.W)) )
+
 
 
   val localDevIndex = Output(UInt(16.W))
@@ -115,47 +115,36 @@ abstract class SlaveParserBase extends Module{
   // val downSinkSel = Reg(Bool())
   // val upSinkSel = Reg(Bool())
 
-  val downFrameInfo  = Reg(new FrameHeader) //下行大包头
-  val upFrameInfo  = Reg(new FrameHeader) //上行大包头
+  // val downFrameInfo  = Reg(new FrameHeader) //下行大包头
+  // val upFrameInfo  = Reg(new FrameHeader) //上行大包头
 
   // val isDownSendBusy = downSendGen.io.frameReq.ready
   // val isUpSendBusy   =   upSendGen.io.frameReq.ready
 
-  val isDownSendPend = RegInit(false.B)
-  val isUpSendPend = RegInit(false.B)
 
-  // val isUpProbePending
 
   //处理主报文
 
-  when( downSendGen.io.frameReq.fire ){
-    isDownSendPend := false.B
-  } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){//下行来了一个普通包
-    isDownSendPend := true.B
-    downFrameInfo := downRecParser.io.frameReq.bits
-  } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){//下行来了一个嗅探包
-    isDownSendPend := true.B
-    downFrameInfo := downRecParser.io.frameReq.bits
-  }
+  // when( downSendGen.io.frameReq.fire ){
+
+  // } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){//下行来了一个普通包
+  //   downFrameInfo := downRecParser.io.frameReq.bits
+  // } .elsewhen( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){//下行来了一个嗅探包
+  //   downFrameInfo := downRecParser.io.frameReq.bits
+  // }
 
   when( upSendGen.io.frameReq.fire ){
-    isUpSendPend := false.B
+
   } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){ //上行来了一个普通包
-    isUpSendPend := true.B
-    upFrameInfo := upRecParser.io.frameReq.bits
+
+    // upFrameInfo := upRecParser.io.frameReq.bits
   }
 
 
-  downSendGen.io.frameReq.valid :=
-    isDownSendPend & downFrameInfo.frameStyle === FRAME_STYLE_COMMON & downRecParser.io.subMsgReq.fire | //下行转发
-    isDownSendPend & downFrameInfo.frameStyle === FRAME_STYLE_PROBE  //下行探针
+  downSendGen.io.frameReq.valid := downRecParser.io.frameReq.fire
+  assert( ~(downSendGen.io.frameReq.valid & ~downSendGen.io.frameReq.ready) )
 
-  // assert( OneHot(isDownSendPend, isDownSendProbe) )
-
-  downSendGen.io.frameReq.bits  := Mux1H(Seq(
-    isDownSendPend -> downFrameInfo,  //下行转发
-    //isDownSendProbe -> probeFrame, //下行探针
-  ))
+  downSendGen.io.frameReq.bits  := downRecParser.io.frameReq.bits
   
 
   val upFrameProbeInfo: FrameHeader = Wire(new FrameHeader)
@@ -164,14 +153,17 @@ abstract class SlaveParserBase extends Module{
   upFrameProbeInfo.frameInfo   := localDevIndex      //其它信息，如probe
 
   upSendGen.io.frameReq.valid :=
-    isUpSendPend & upRecParser.io.subMsgReq.fire |     //上行转发
-    isAckProbe // 上行探针
+  (upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON) |
+  isAckProbe
 
-  assert( ~(isUpSendPend & isAckProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )
+  assert( ~(upSendGen.io.frameReq.valid & ~upSendGen.io.frameReq.ready) )
+
+
+  assert( ~(upRecParser.io.frameReq.fire & isAckProbe), "Assert Failed, Check Softwave, Probe is Sent while transfering!\n" )
 
   upSendGen.io.frameReq.bits := Mux1H(Seq(
-    isUpSendPend   -> upFrameInfo,      //上行转发
-    isAckProbe -> upFrameProbeInfo, //上行探针
+    upRecParser.io.frameReq.fire -> upRecParser.io.frameReq.bits,      //上行转发
+    isAckProbe                   -> upFrameProbeInfo, //上行探针
   ))
 
 
@@ -376,6 +368,7 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
     localDevIndex := downRecParser.io.subMsgReq.bits.workCnt + 1.U
     isDevOnLeftModify  := false.B
     indexOfLeftDev     := downRecParser.io.subMsgReq.bits.workCnt
+    indexOfRightDev    := Mux(isLastDevice, 0.U, downRecParser.io.subMsgReq.bits.workCnt + 2.U)
 
     isDevOnRightModify := false.B
     when( isDownRecPing ){
@@ -384,6 +377,10 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
       downSubMsgInfo(1).workCnt := downRecParser.io.subMsgReq.bits.workCnt + 1.U
     }
   }
+
+
+  //上行接收 获取右侧索引号
+
 }
 
 
@@ -559,14 +556,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   io.sram_r(3).addrr := readSMAddr(10,0)
 
 
-  io.dSMenq(0) := isWrite & isWRSM0 & io.trigAddr(0) === addrw(10,0)
-  io.uSMdeq(0) := isRead  & isRDSM1 & io.trigAddr(1) === readSMAddr(10,0)
-  io.dSMenq(1) := isWrite & isWRSM2 & io.trigAddr(2) === addrw(10,0)
-  io.uSMdeq(1) := isRead  & isRDSM3 & io.trigAddr(3) === readSMAddr(10,0)
-  io.dSMenq(2) := isWrite & isWRSM4 & io.trigAddr(4) === addrw(10,0)
-  io.uSMdeq(2) := isRead  & isRDSM5 & io.trigAddr(5) === readSMAddr(10,0)
-  io.dSMenq(3) := isWrite & isWRSM6 & io.trigAddr(6) === addrw(10,0)
-  io.uSMdeq(3) := isRead  & isRDSM7 & io.trigAddr(7) === readSMAddr(10,0)
+  io.dSMenq(0) := isWrite & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0)
+  io.uSMdeq(0) := isRead  & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === readSMAddr(10,0)
+  io.dSMenq(1) := isWrite & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0)
+  io.uSMdeq(1) := isRead  & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === readSMAddr(10,0)
+  io.dSMenq(2) := isWrite & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0)
+  io.uSMdeq(2) := isRead  & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === readSMAddr(10,0)
+  io.dSMenq(3) := isWrite & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0)
+  io.uSMdeq(3) := isRead  & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === readSMAddr(10,0)
 
 
 }
@@ -673,14 +670,15 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
 
 
 
-  val isReadyToProbe_Pending = RegInit(false.B)
+  // val isReadyToProbe_Pending = RegInit(false.B)
 
   when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
-    isReadyToProbe_Pending := true.B
+    isReadyToProbe := true.B
+    assert( downSendGen.io.stateCurr === STATE_IDLE )
   } .elsewhen( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
-    isReadyToProbe_Pending := false.B
+    isReadyToProbe := false.B
   } .elsewhen( isWatchDogOverflow ){
-    isReadyToProbe_Pending := false.B
+    isReadyToProbe := false.B
   }
 
   when( downRecParser.io.frameReq.fire & downRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //下行来了一个嗅探包
@@ -691,12 +689,12 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
 
 
 
-  val isLastDevice_Pending = RegInit(true.B)
+  // val isLastDevice = RegInit(true.B)
 
   when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_PROBE ){ //上行来了一个嗅探包
-    isLastDevice_Pending := false.B
+    isLastDevice := false.B
   } .elsewhen( isWatchDogOverflow ){
-    isLastDevice_Pending := true.B
+    isLastDevice := true.B
   }
 
 
@@ -744,13 +742,13 @@ trait SlaveParserProbe{ this: SlaveParserBase =>
   io.isLoop := isLastDevice & ~isReadyToProbe
 
 
-  when( isLastDevice =/= isLastDevice_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){
-    isLastDevice := isLastDevice_Pending
-  }
+  // when( isLastDevice =/= isLastDevice_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){
+  //   isLastDevice := isLastDevice_Pending
+  // }
 
-  when( isReadyToProbe =/= isReadyToProbe_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){
-    isReadyToProbe := isReadyToProbe_Pending
-  }
+  // when( isReadyToProbe =/= isReadyToProbe_Pending & ~downSendGen.io.send.valid & ~io.downOut.valid & ~io.upIn.valid ){
+  //   isReadyToProbe := isReadyToProbe_Pending
+  // }
 }
 
 class SlaveParser extends SlaveParserBase
diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala
index 59d4d44..bb618cd 100644
--- a/src/main/scala/backBoard/shin/SlaveSendGen.scala
+++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala
@@ -20,6 +20,7 @@ class SlaveSendGenIO extends Bundle{
   val send = Decoupled(new AXIS_Bundle(8))
 
   val isError = Output(Bool())
+  val stateCurr = Output(UInt(3.W))
 }
 
 
@@ -40,11 +41,11 @@ class SlaveSendGen extends Module{
   val STATE_SUBMSG_DATA     = 3.U
   val STATE_CRC             = 4.U //CRC校验
   val STATE_ERROR           = 5.U
-  // val STATE_WAIT            = 6.U
+  val STATE_WAIT            = 6.U
 
 
   val stateNext = Wire(UInt(3.W))
-  val stateCurr = RegNext(stateNext, STATE_IDLE)
+  val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
 
   io.isError := stateCurr === STATE_ERROR
 
@@ -116,18 +117,19 @@ class SlaveSendGen extends Module{
     (stateCurr === STATE_IDLE)          -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
     (stateCurr === STATE_FRAME_HEADER)  -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, Mux( 
       frameInfo.frameStyle === FRAME_STYLE_COMMON,
-        Mux(io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR),
+        Mux(io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
         STATE_CRC ),
       STATE_FRAME_HEADER), STATE_FRAME_HEADER ),
     (stateCurr === STATE_SUBMSG_HEADER) -> Mux( io.send.fire, Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER), STATE_SUBMSG_HEADER),
     (stateCurr === STATE_SUBMSG_DATA)   -> Mux( io.send.fire, 
       Mux( lengthCnt === subMsgInfoSel.length-1.U,    //已经发送完成该子报文
         Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC
-          Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ) ), //主报文长度未到，进下一个子报文
+          Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT ) ), //主报文长度未到，进下一个子报文
         STATE_SUBMSG_DATA
       ), STATE_SUBMSG_DATA ),
     (stateCurr === STATE_CRC)           -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
     (stateCurr === STATE_ERROR)         -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
+    (stateCurr === STATE_WAIT)          -> Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
   ))
 
   io.data(0).ready := io.send.fire & (stateCurr === STATE_SUBMSG_DATA) & (subMsgInfoSel.source === 0.U)
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index fab86c6..2759d16 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -55,8 +55,8 @@ ShinTop s_ShinTop_Mst(
   .io_oqspi_csn(spi_csn[10]),
 
   .io_rsp_valid(isResp),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 ShinTop s_ShinTop_slv0(
@@ -87,8 +87,8 @@ ShinTop s_ShinTop_slv0(
   .io_oqspi_csn(spi_csn[11]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 ShinTop s_ShinTop_slv1(
@@ -119,8 +119,8 @@ ShinTop s_ShinTop_slv1(
   .io_oqspi_csn(spi_csn[12]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 ShinTop s_ShinTop_slv2(
@@ -151,8 +151,8 @@ ShinTop s_ShinTop_slv2(
   .io_oqspi_csn(spi_csn[13]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 ShinTop s_ShinTop_slv3(
@@ -183,8 +183,8 @@ ShinTop s_ShinTop_slv3(
   .io_oqspi_csn(spi_csn[14]),
 
   .io_rsp_valid(),
-  .io_rsp_bits_isError(),
-  .io_rsp_bits_length()
+  .io_rsp_bits_isError()
+  // .io_rsp_bits_length()
 );
 
 
@@ -507,24 +507,25 @@ initial begin
     spi_trans( (16'h00c0), (`SPI_READ), (6), (`IF_IDX(4)) );
 
     $fdisplay(spidata_file, "--->>>嗅探");
-    //设置SM1在写入0x3地址触发enq
-    txBuf[0+3] = 8'h03;
+    //设置SM1在写入0x4 len 触发enq
+    //设置SM0在读出0x4 len 触发deq
+    txBuf[0+3] = 8'h04;
     txBuf[1+3] = 8'h00;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     //无子报文
     `include "detect_pkt.vh"
     spi_trans( (16'h1000), (`SPI_WRITE), (4), (`IF_IDX(0)) ); //写入SM1
 
     //发布请求
-    txBuf[0+3] = 8'h04;
-    txBuf[1+3] = 8'h00;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
     @(posedge isResp) #5 begin end
 
+    rxBuf[0+3] = 0;
+    spi_trans( (16'h803), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
+
   end
 
 
@@ -553,10 +554,11 @@ initial begin
 
 
     $fdisplay(spidata_file, "--->>>设置顺序地址");
-    //设置SM1在写入0xd地址触发enq
-    txBuf[0+3] = 8'h0d;
+    //设置SM1在写入0xe len触发enq
+    txBuf[0+3] = 8'h0e;
     txBuf[1+3] = 8'h00;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     txBuf[0+3] = 8'h00;
     txBuf[1+3] = 8'ha0;//heeader length 10
@@ -579,15 +581,14 @@ initial begin
     spi_trans( (16'h1000), (`SPI_WRITE), (14), (`IF_IDX(0)) ); //写入SM1
 
 
-
     //发布请求
-    txBuf[0+3] = 8'h0e;
-    txBuf[1+3] = 8'h00;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
     @(posedge isResp) #5 begin end
+
+    rxBuf[0+3] = 0;
+    spi_trans( (16'h80D), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
+
   end
 
 
@@ -661,23 +662,22 @@ initial begin
   $display("read&write @ %d", s_ShinTop_Mst.interface__io_cReg_timeStamp);
   begin
 
-    //设置SM1在写入516地址触发enq
-    txBuf[0+3] = 8'h03;
+    //设置SM1在写入516 len触发enq
+    txBuf[0+3] = 8'h04;
     txBuf[1+3] = 8'h02;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     `include "seq_pkt.vh"
     spi_trans( (16'h1000), (`SPI_WRITE), (516), (`IF_IDX(0)) ); //写入SM1
     //发布请求
-    txBuf[0+3] = 8'h04;
-    txBuf[1+3] = 8'h02;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
     @(posedge isResp) #5 begin end
   end
 
+    spi_trans( (16'ha03), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
+
 
 
   // 同步
@@ -701,10 +701,11 @@ initial begin
 
 
 
-    //设置SM1在写入0x3地址触发enq
-    txBuf[0+3] = 8'h17;
+    //设置SM1在写入 0x18 len触发enq
+    txBuf[0+3] = 8'h18;
     txBuf[1+3] = 8'h00;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     `include "sync_pkt.vh"
     spi_trans( (16'h1000), (`SPI_WRITE), (24), (`IF_IDX(0)) ); //写入SM1
@@ -715,13 +716,12 @@ initial begin
     spi_trans( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(0)) ); //写入替换时间戳替换地址寄存器
 
     //发布请求
-    txBuf[0+3] = 8'h18;
-    txBuf[1+3] = 8'h00;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
-    @(posedge isResp) #5 begin end
+    @(posedge isResp) #5 begin
+      spi_trans( (16'h817), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
+    end
+
 
     //清除替换时间戳替换地址
     txBuf[0+3] = 8'h00;
@@ -732,27 +732,25 @@ initial begin
 
     //设定sync信号
 
-    //设置SM1在写入51地址触发enq
-    txBuf[0+3] = 8'd51;
+    //设置SM1在写入52 len触发enq
+    txBuf[0+3] = 8'd52;
     txBuf[1+3] = 8'h00;
-    spi_trans( (16'h0202), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) );
+    spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) );
 
     `include "sync_sig_pkt.vh"
     spi_trans( (16'h1000), (`SPI_WRITE), (52), (`IF_IDX(0)) ); //写入SM1
 
     //发布请求
-    txBuf[0+3] = 8'd52;
-    txBuf[1+3] = 8'h00;
-    spi_trans( (16'h21), (`SPI_WRITE), (2), (`IF_IDX(0)) );//写入长度
-
     txBuf[0+3] = 8'h01;
     spi_trans( (16'h20), (`SPI_WRITE), (1), (`IF_IDX(0)) );//发送SM0 接收SM0, 请求发送
     @(posedge isResp) #5 begin end
 
+    spi_trans( (16'h833), (`SPI_READ), (1), (`IF_IDX(0)) );//读一下SM0的切换地址，将fifo弹出
   end
 
+
   //清脉冲
-    //设置SM1在写入19地址触发enq
     txBuf[0+3] = 0;  //负载0x122 sync0脉冲宽度
     txBuf[1+3] = 0;  //负载0x123
     txBuf[2+3] = 0;  //负载0x124 sync1脉冲宽度
diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py
index b9b39e8..09b856c 100755
--- a/tb/shinTest/gen_pkt.py
+++ b/tb/shinTest/gen_pkt.py
@@ -140,15 +140,18 @@ if __name__ == '__main__':
 
     #subPkt参数：索引、索引类型、地址、命令、长度、数据
     data = bytearray(b"\0" * 0x28)
-    data[0] = 0xff
-    data[16] = 0x90
-    data[17] = 0x88
-    data[24] = 0xff
-    data[25] = 0x0f
-    data[28] = 0x0a
+    data[0] = 0xff  #地址0x120
+    
+    data[16] = 0x90 #地址0x130, sync同步点
+    data[17] = 0x88 #地址0x131
+    
+    data[24] = 0xff #地址0x138, sync周期 4B
+    data[25] = 0x0f #地址0x139
+    
+    data[28] = 0x0a #sync1偏移
     data[29] = 0x0
 
-    data[36] = 0x0
+    data[36] = 0x0  #sync3偏移
     data[37] = 0x01
     
     genPkt.addSubPkt(0x2, 0, 0x120, 0x1, 0x28, data)