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test pass

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This commit is contained in:
RuigeLee
2023-08-31 17:39:12 +08:00
parent d226487a5e
commit 145db92202
4 changed files with 142 additions and 41 deletions
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27
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -45,10 +45,12 @@ class BackBoardMstBase extends RawModule{
val slvNum = Wire(UInt(5.W))
mirrorDown.io.clock := io.ides_pclk.asBool
mirrorDown.io.reset := io.reset.asBool
mirrorUp.io.clock := io.ides_pclk.asBool
mirrorUp.io.reset := io.reset.asBool
mirrorDown.io.clockw := io.ides_pclk.asBool
mirrorDown.io.clockr := io.oser_pclk.asBool
mirrorUp.io.clockw := io.oser_pclk.asBool
mirrorUp.io.clockr := io.ides_pclk.asBool
}
@@ -186,30 +188,35 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
assert(false.B)
}
}
withClockAndReset( io.oser_pclk.asClock, io.reset ){
val addrr = RegInit(0.U(11.W))
val addrw = RegInit(0.U(11.W))
when( trigger_wire ){
addrw := 0.U
} .elsewhen( lvdsMst.io.rx_data_valid ){
} .elsewhen( lvdsMst.io.rx_data_valid & ~isSync){
assert( (stateCur_wire === 2.U) || (stateCur_wire === 3.U) )
addrw := addrw + 1.U
}
when( trigger_wire ){
addrr := 0.U
} .elsewhen( lvdsMst.io.tx_data_ready ){
} .elsewhen( lvdsMst.io.tx_data_ready & ~isSync){
addrr := addrr + 1.U
}
mirrorDown.io.enr := (stateCur_wire === 1.U || stateCur_wire === 2.U)
mirrorDown.io.enr := (stateCur_wire === 1.U || stateCur_wire === 2.U) & ~isSync
lvdsMst.io.tx_data_in := mirrorDown.io.datar
mirrorDown.io.addrr := addrr
mirrorUp.io.enw := lvdsMst.io.rx_data_valid
mirrorUp.io.enw := lvdsMst.io.rx_data_valid & ~isSync
mirrorUp.io.dataw := lvdsMst.io.rx_data_out
mirrorUp.io.addrw := addrw

10
src/main/scala/backBoard/BackBoardSlv.scala
View File

@@ -105,7 +105,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
withClockAndReset( io.oser_pclk.asClock, io.reset ){
val upCnt = RegInit(0.U(6.W))
val upCnt = RegInit(31.U(6.W))
val upTimeoutEn = RegInit( false.B )
val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
@@ -126,19 +126,21 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
when( upTimeout ){
upTimeoutEn := false.B
} .elsewhen( upCnt === 32.U ){
} .elsewhen( upCnt === 31.U ){
upTimeoutEn := false.B
} .elsewhen(upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready){
} .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
upTimeoutEn := true.B
}
when( upTimeout ){
upCnt := 0.U
}.elsewhen( upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready ){
}.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
when(upCnt === 31.U){
upCnt := 0.U
} .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
upCnt := upCnt + 1.U
}
}
}
}

4
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -10,7 +10,9 @@ class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with
val oe = IO(Output(UInt(32.W)))
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val upReg = Reg(Vec(32, UInt(8.W))); upRegWire := upReg
// val upReg = Reg(Vec(32, UInt(8.W)))
val upReg = RegInit(VecInit((0 until 32).map{i => i.U(8.W)}))
upRegWire := upReg
out := Cat( (0 until 4).map{i => downRegWire(i)}.reverse )
oe := Cat( (4 until 8).map{i => downRegWire(i)}.reverse )

138
src/main/scala/backBoard/MirrorSRAM.scala
View File

@@ -4,41 +4,131 @@ import chisel3._
import chisel3.util._
class MirrorSRAM(dw: Int, cl: Int) extends RawModule {
def line_w = log2Ceil(cl)
val io = IO(new Bundle{
val addrr = Input(UInt(line_w.W))
val addrw = Input(UInt(line_w.W))
// class MirrorSRAM(dw: Int, cl: Int) extends RawModule {
// def line_w = log2Ceil(cl)
// val io = IO(new Bundle{
// val addrr = Input(UInt(line_w.W))
// val addrw = Input(UInt(line_w.W))
val dataw = Input( UInt(dw.W) )
val datar = Output( UInt(dw.W) )
// val dataw = Input( UInt(dw.W) )
// val datar = Output( UInt(dw.W) )
// val enw = Input(Bool())
// val enr = Input(Bool())
// val clock = Input(Bool())
// val reset = Input(Bool())
// })
// withClockAndReset( io.clock.asClock, io.reset ){
// val mem = SyncReadMem( cl, UInt(dw.W) )
// io.datar := DontCare
// when( io.enr ) {
// io.datar := mem.read( io.addrr )
// }
// when( io.enw ) {
// mem.write( io.addrw, io.dataw )
// }
// }
// }
// val addrr = Input(UInt(line_w.W))
// val addrw = Input(UInt(line_w.W))
// val dataw = Input( UInt(dw.W) )
// val datar = Output( UInt(dw.W) )
// val enw = Input(Bool())
// val enr = Input(Bool())
// val clock = Input(Bool())
// val reset = Input(Bool())
class MirrorSRAM(dw: Int, cl: Int) extends BlackBox with HasBlackBoxInline {
require(dw == 8)
require(cl == 2048)
class MirrorSRAMIO extends Bundle{
val addrr = Input(UInt(11.W))
val addrw = Input(UInt(11.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
val clock = Input(Bool())
val reset = Input(Bool())
})
val clockr = Input(Bool())
val clockw = Input(Bool())
withClockAndReset( io.clock.asClock, io.reset ){
val mem = SyncReadMem( cl, UInt(dw.W) )
io.datar := DontCare
when( io.enr ) {
io.datar := mem.read( io.addrr )
}
when( io.enw ) {
mem.write( io.addrw, io.dataw )
}
val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
setInline("MirrorSRAM.v",
"""
| module MirrorSRAM(
| input [7:0] dataw,
| input [10:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [10:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [7:0] ram[0:2047];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 2048; i = i + 1 ) begin
| ram[i] = $random;
| end
|
| data_r_reg = $random;
| end
|
|endmodule
""".stripMargin)
}
}