test pass

src/main/scala/backBoard/MirrorSRAM.scala

@@ -4,40 +4,120 @@ import chisel3._
 import chisel3.util._
 
 
-class MirrorSRAM(dw: Int,  cl: Int) extends RawModule {
-  def line_w   = log2Ceil(cl)
-  val io = IO(new Bundle{
-    val addrr  = Input(UInt(line_w.W))
-    val addrw  = Input(UInt(line_w.W))
+// class MirrorSRAM(dw: Int,  cl: Int) extends RawModule {
+//   def line_w   = log2Ceil(cl)
+//   val io = IO(new Bundle{
+//     val addrr  = Input(UInt(line_w.W))
+//     val addrw  = Input(UInt(line_w.W))
 
-    val dataw = Input( UInt(dw.W) )
-    val datar = Output( UInt(dw.W) )
-    val enw   = Input(Bool())
-    val enr   = Input(Bool())
+//     val dataw = Input( UInt(dw.W) )
+//     val datar = Output( UInt(dw.W) )
+//     val enw   = Input(Bool())
+//     val enr   = Input(Bool())
 
-    val clock = Input(Bool())
-    val reset = Input(Bool())
-  })
+//     val clock = Input(Bool())
+//     val reset = Input(Bool())
+//   })
 
 
-  withClockAndReset( io.clock.asClock, io.reset ){
-    val mem = SyncReadMem( cl, UInt(dw.W) )
+//   withClockAndReset( io.clock.asClock, io.reset ){
+//     val mem = SyncReadMem( cl, UInt(dw.W) )
 
 
 
 
-    io.datar := DontCare
-    when( io.enr ) {
-      io.datar := mem.read( io.addrr )
-    } 
-    when( io.enw ) {
-      mem.write( io.addrw, io.dataw )
-    }
+//     io.datar := DontCare
+//     when( io.enr ) {
+//       io.datar := mem.read( io.addrr )
+//     } 
+//     when( io.enw ) {
+//       mem.write( io.addrw, io.dataw )
+//     }
+//   }
+
+
+
+
+// }
+
+
+
+
+
+
+
+//     val addrr  = Input(UInt(line_w.W))
+//     val addrw  = Input(UInt(line_w.W))
+
+//     val dataw = Input( UInt(dw.W) )
+//     val datar = Output( UInt(dw.W) )
+//     val enw   = Input(Bool())
+//     val enr   = Input(Bool())
+
+//     val clock = Input(Bool())
+//     val reset = Input(Bool())
+
+
+class MirrorSRAM(dw: Int,  cl: Int) extends BlackBox with HasBlackBoxInline {
+  require(dw == 8)
+  require(cl == 2048)
+  class MirrorSRAMIO extends Bundle{
+      val addrr  = Input(UInt(11.W))
+      val addrw  = Input(UInt(11.W))
+
+      val dataw = Input( UInt(8.W) )
+      val datar = Output( UInt(8.W) )
+      val enw   = Input(Bool())
+      val enr   = Input(Bool())
+
+      val clockr = Input(Bool())
+      val clockw = Input(Bool())
+
   }
+  val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
 
-
-
-
+ setInline("MirrorSRAM.v",
+              """
+      | module MirrorSRAM(
+      |  	input [7:0]  dataw,
+      |  	input [10:0] addrw,
+      |  	input enw,
+      |  
+      |  	output [7:0] datar,
+      |  	input [10:0] addrr,
+      |  	input enr,
+      |  
+      |  	input clockr,
+      |   input clockw
+      |  );
+      |  
+      |  	reg [7:0] ram[0:2047];
+      |  	reg [7:0] data_r_reg;
+      |  
+      |  			always @(posedge clockw) begin
+      |  				if(enw) begin
+      |  					ram[addrw] <= #1 dataw;					
+      |  				end
+      |       end
+      |  
+      |       always @(posedge clockr) begin
+      |  				if(enr) begin
+      |  					data_r_reg <= #1 ram[addrr];
+      |  				end
+      |  			end
+      |  
+      |  	assign datar = data_r_reg;
+      |  
+      |  initial begin
+      |  	for ( integer i = 0; i < 2048; i = i + 1 ) begin
+      |  		ram[i] = $random;
+      |  	end
+      |  
+      |  	data_r_reg = $random;
+      |  end
+      |   
+      |endmodule
+    """.stripMargin)
 }
 
 
@@ -45,6 +125,16 @@ class MirrorSRAM(dw: Int,  cl: Int) extends RawModule {
 
 
 
+
+
+
+
+
+
+
+
+
+
 // class MirrorSRAMIO extends Bundle{
 //   val datar = Output(UInt(8.W))
 //   val dataw = Input(UInt(8.W))