ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

test pass

Browse Source
This commit is contained in:
RuigeLee
2023-08-31 17:39:12 +08:00
parent d226487a5e
commit 145db92202
4 changed files with 142 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/backBoard/LocalRegisters.scala
View File

@@ -10,7 +10,9 @@ class BackBoardSlvDigitalIO extends BackBoardSlvBase with BackBoardSlvDown with
val oe = IO(Output(UInt(32.W)))
withClockAndReset( io.ides_pclk.asClock, io.reset ){
val upReg = Reg(Vec(32, UInt(8.W))); upRegWire := upReg
// val upReg = Reg(Vec(32, UInt(8.W)))
val upReg = RegInit(VecInit((0 until 32).map{i => i.U(8.W)}))
upRegWire := upReg
out := Cat( (0 until 4).map{i => downRegWire(i)}.reverse )
oe := Cat( (4 until 8).map{i => downRegWire(i)}.reverse )