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test pass

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RuigeLee
2023-08-31 17:39:12 +08:00
parent d226487a5e
commit 145db92202
4 changed files with 142 additions and 41 deletions
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14
src/main/scala/backBoard/BackBoardSlv.scala
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@@ -105,7 +105,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
withClockAndReset( io.oser_pclk.asClock, io.reset ){
val upCnt = RegInit(0.U(6.W))
val upCnt = RegInit(31.U(6.W))
val upTimeoutEn = RegInit( false.B )
val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
val ( _, upTimeout ) = Counter( Range( 0,1023 ), upTimeoutEn, upTimeoutRst )
@@ -126,18 +126,20 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
when( upTimeout ){
upTimeoutEn := false.B
} .elsewhen( upCnt === 32.U ){
} .elsewhen( upCnt === 31.U ){
upTimeoutEn := false.B
} .elsewhen(upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready){
} .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
upTimeoutEn := true.B
}
when( upTimeout ){
upCnt := 0.U
}.elsewhen( upCnt === 32.U & lvdsSlv.io.upstream_tx_data_ready ){
upCnt := 0.U
}.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
upCnt := upCnt + 1.U
when(upCnt === 31.U){
upCnt := 0.U
} .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
upCnt := upCnt + 1.U
}
}
}