test pass

src/main/scala/backBoard/BackBoardMst.scala

@@ -45,10 +45,12 @@ class BackBoardMstBase extends RawModule{
     val slvNum  = Wire(UInt(5.W))
 
 
-  mirrorDown.io.clock := io.ides_pclk.asBool
-  mirrorDown.io.reset := io.reset.asBool
-  mirrorUp.io.clock := io.ides_pclk.asBool
-  mirrorUp.io.reset := io.reset.asBool
+  mirrorDown.io.clockw := io.ides_pclk.asBool
+  mirrorDown.io.clockr := io.oser_pclk.asBool
+
+  mirrorUp.io.clockw := io.oser_pclk.asBool
+  mirrorUp.io.clockr := io.ides_pclk.asBool
+
 }
 
 
@@ -186,30 +188,35 @@ trait BackBoardMstLVDS{ this: BackBoardMstBase =>
 
       assert(false.B)
     }
-  }
 
-  withClockAndReset( io.oser_pclk.asClock, io.reset ){
+
+
+
+
+
+
+
     val addrr = RegInit(0.U(11.W))
     val addrw = RegInit(0.U(11.W))
 
     when( trigger_wire ){
       addrw := 0.U
-    } .elsewhen( lvdsMst.io.rx_data_valid ){
+    } .elsewhen( lvdsMst.io.rx_data_valid & ~isSync){
       assert( (stateCur_wire === 2.U) || (stateCur_wire === 3.U) )
       addrw := addrw + 1.U
     }
 
     when( trigger_wire ){
       addrr := 0.U
-    } .elsewhen( lvdsMst.io.tx_data_ready ){
+    } .elsewhen( lvdsMst.io.tx_data_ready & ~isSync){
       addrr := addrr + 1.U
     }
 
-    mirrorDown.io.enr := (stateCur_wire === 1.U || stateCur_wire === 2.U)
+    mirrorDown.io.enr := (stateCur_wire === 1.U || stateCur_wire === 2.U) & ~isSync
     lvdsMst.io.tx_data_in := mirrorDown.io.datar
     mirrorDown.io.addrr := addrr
     
-    mirrorUp.io.enw    := lvdsMst.io.rx_data_valid
+    mirrorUp.io.enw    := lvdsMst.io.rx_data_valid & ~isSync
     mirrorUp.io.dataw := lvdsMst.io.rx_data_out
     mirrorUp.io.addrw := addrw