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合并spi的最新修改

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This commit is contained in:
bacon
2025-05-17 12:27:31 +08:00
parent 2f8be794c0 c4daca834c
commit 131d90c996
3 changed files with 74 additions and 53 deletions
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4
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -406,7 +406,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
))
datar := MuxCase( 0.U, Array(
((addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrSel), 0.U, isEnR ),
((addrSel & "hFF00".U) === "h0000".U) -> AcquireReg(addr = addrSel),
((addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
((addrSel & "hFF00".U) === "h1000".U) -> 0.U,
((addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
@@ -585,7 +585,7 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
// io.lvds.isEnW = Output(Bool())
// io.lvds.isEnR = Output(Bool())
io.lvds.datar := RegEnable( AcquireReg(addr = io.lvds.addrSel), 0.U, io.lvds.isEnR )
io.lvds.datar := AcquireReg(addr = io.lvds.addrSel)
when( io.lvds.isEnW & isSlvMode ){

31
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -48,7 +48,7 @@ abstract class SpiInterfaceBase extends Module{
val addrSel = Reg(UInt(16.W)); io.addrSel := addrSel
val addrSel = Reg(UInt(16.W))
val spiCmd = Reg(UInt(8.W))
val isSpiWrite = spiCmd === 0.U
@@ -58,9 +58,14 @@ abstract class SpiInterfaceBase extends Module{
val byteSel = Reg(UInt(12.W))
io.isEnR := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & exReg === 1.U & byteSel === 3.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U)
io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U
io.dataw := exReg
io.addrSel :=
Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
when( shiftCSn(2) & ~shiftCSn(1) ){
byteSel := 0.U
@@ -114,18 +119,12 @@ class SSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U & (byteSel === 1.U || byteSel === 2.U) ){ //CS为低，且SCK上跳补一拍 的第0bit
exReg := 0.U
} .otherwise{
when( isSpiWrite ){
} .elsewhen( isSpiWrite ){
exReg := 0.U
} .elsewhen( isSpiRead ){
exReg := io.datar
} .otherwise{
assert(false.B, "Assert Failed, empty CMD!\n")
}
}
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(6 ,0), shiftMOSI(1) )
}
@@ -150,18 +149,12 @@ class QSpiInterface extends SpiInterfaceBase{
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 //第一个byte
exReg := 0.U
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U ){ //CS为低，且SCK上跳补一拍 的第0bit
when( byteSel === 1.U || byteSel === 2.U ){ //第1、2byte
} .elsewhen( isSckPosedgeNext(1) & ~shiftCSn(2) & bitSel === 0.U & ( byteSel === 1.U || byteSel === 2.U) ){ //CS为低，且SCK上跳补一拍 的第0bit
exReg := 0.U
} .otherwise{
when( isSpiWrite ){
} .elsewhen( io.isEnW ){
exReg := 0.U
} .elsewhen( isSpiRead ){
} .elsewhen( io.isEnR ){
exReg := io.datar
} .otherwise{
assert(false.B, "Assert Failed, empty CMD!\n")
}
}
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
exReg := Cat( exReg(3,0), shiftMOSI(1) )
}

74
tb/shinTest/ShinTopSpiTb.v
View File

@@ -14,12 +14,12 @@ module ShinTopSpiTb(
wire spi_sck;
wire spi_mosi;
wire spi_miso;
wire [4:0] spi_miso;
reg [14:0] spi_csn;
wire qspi_sck;
wire [3:0] qspi_mosi;
wire [3:0] qspi_miso;
wire [40-1:0] qspi_miso;
wire isResp;
@@ -38,19 +38,19 @@ ShinTop s_ShinTop_Mst(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_miso(qspi_miso[3:0]),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[0]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso),
.io_ospi_miso(spi_miso[0]),
.io_ospi_csn (spi_csn[5]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_miso(qspi_miso[4*5+3:4*5]),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[10]),
@@ -71,18 +71,18 @@ ShinTop s_ShinTop_slv0(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_miso(qspi_miso[4*1+3:4*1]),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[1]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso),
.io_ospi_miso(spi_miso[1]),
.io_ospi_csn (spi_csn[6]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_miso(qspi_miso[4*6+3:4*6]),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[11]),
@@ -103,18 +103,18 @@ ShinTop s_ShinTop_slv1(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_miso(qspi_miso[4*2+3:4*2]),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[2]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso),
.io_ospi_miso(spi_miso[2]),
.io_ospi_csn (spi_csn[7]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_miso(qspi_miso[4*7+3:4*7]),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[12]),
@@ -135,18 +135,18 @@ ShinTop s_ShinTop_slv2(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_miso(qspi_miso[4*3+3:4*3]),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[3]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso),
.io_ospi_miso(spi_miso[3]),
.io_ospi_csn (spi_csn[8]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_miso(qspi_miso[4*8+3:4*8]),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[13]),
@@ -167,18 +167,18 @@ ShinTop s_ShinTop_slv3(
.io_iqspi_sck(qspi_sck),
.io_iqspi_mosi(qspi_mosi),
.io_iqspi_miso(qspi_miso),
.io_iqspi_miso(qspi_miso[4*4+3:4*4]),
.io_iqspi_isDirIn(),
.io_iqspi_csn(spi_csn[4]),
.io_ospi_sck (spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso),
.io_ospi_miso(spi_miso[4]),
.io_ospi_csn (spi_csn[9]),
.io_oqspi_sck(qspi_sck),
.io_oqspi_mosi(qspi_mosi),
.io_oqspi_miso(qspi_miso),
.io_oqspi_miso(qspi_miso[4*9+3:4*9]),
.io_oqspi_isDirIn(),
.io_oqspi_csn(spi_csn[14]),
@@ -274,6 +274,24 @@ end
assign spi_mosi = exChangeReg[7];
assign qspi_mosi = exChangeReg[7:4];
wire [3:0] qspi_mux_miso =
( qspi_miso[4*0+3:4*0] & ~{4{spi_csn[ 0]}}) |
( qspi_miso[4*1+3:4*1] & ~{4{spi_csn[ 1]}}) |
( qspi_miso[4*2+3:4*2] & ~{4{spi_csn[ 2]}}) |
( qspi_miso[4*3+3:4*3] & ~{4{spi_csn[ 3]}}) |
( qspi_miso[4*4+3:4*4] & ~{4{spi_csn[ 4]}}) |
( qspi_miso[4*5+3:4*5] & ~{4{spi_csn[10]}}) |
( qspi_miso[4*6+3:4*6] & ~{4{spi_csn[11]}}) |
( qspi_miso[4*7+3:4*7] & ~{4{spi_csn[12]}}) |
( qspi_miso[4*8+3:4*8] & ~{4{spi_csn[13]}}) |
( qspi_miso[4*9+3:4*9] & ~{4{spi_csn[14]}});
wire spi_mux_miso =
( spi_miso[0] & ~spi_csn[5] ) |
( spi_miso[1] & ~spi_csn[6] ) |
( spi_miso[2] & ~spi_csn[7] ) |
( spi_miso[3] & ~spi_csn[8] ) |
( spi_miso[4] & ~spi_csn[9] );
reg isReq = 0;
reg isBusy = 0;
@@ -315,13 +333,20 @@ always @(posedge sck) begin
if( &bitCnt ) begin
byteCnt <= byteCnt +1;
transCnt <= transCnt + 1;
rxBuf[byteCnt] <= exChangeReg;
rxBuf[byteCnt] <= isQspi ? {exChangeReg[3:0], qspi_mux_miso} : {exChangeReg[6:0], spi_mux_miso};
if( txBuf[2] === 1 & nextByteCnt >= 4) begin
$display("spi read out @ %x", exChangeReg);
end
if( txBuf[2] === 1 & nextByteCnt >= 3) begin
exChangeReg <= isQspi ? {exChangeReg[3:0], qspi_mux_miso} : {exChangeReg[6:0], spi_mux_miso};
end else begin
exChangeReg <= txBuf[nextByteCnt];
end
end else begin
if( isQspi ) begin
exChangeReg <= {exChangeReg[3:0], qspi_miso};
exChangeReg <= {exChangeReg[3:0], qspi_mux_miso};
end else begin
exChangeReg <= {exChangeReg[6:0], spi_miso};
exChangeReg <= {exChangeReg[6:0], spi_mux_miso};
end
end
@@ -522,8 +547,6 @@ initial begin
// 顺序索引
#50000
#50000
@@ -611,6 +634,11 @@ initial begin
end
//测试
spi_trans( (16'hc0), (`SPI_READ), (6), (3) );//发送SM0 接收SM0, 请求发送
//读写
#50000
#50000
@@ -782,7 +810,7 @@ initial begin
//写入替换时间戳替换地址
txBuf[0+3] = 8'h0c;
txBuf[1+3] = 8'hc0;
spi_trans( (16'h25), (`SPI_WRITE), (2), (`IF_IDX(0)) ); //写入替换时间戳替换地址寄存器
spi_trans( (16'h24), (`SPI_WRITE), (2), (`IF_IDX(0)) ); //写入替换时间戳替换地址寄存器
//发布请求
txBuf[0+3] = 8'h18;