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代码清理

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This commit is contained in:
Ruige Lee
2025-07-17 17:22:08 +08:00
parent 1791a54dae
commit 1319027c9e
1 changed files with 0 additions and 44 deletions
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44
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -28,27 +28,6 @@ abstract class CDRInBase extends Module{
trait CDRInOverSample{ this: CDRInBase =>
val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
// val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
// val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
// val isArbLock = RegInit(false.B)
// for( i <- 0 until sampleRate ){
// arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
// when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
// isArbLock := true.B
// arbSel := i.U
// }
// }
// when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
// isArbLock := false.B
// }
// val syncSerDat =
// Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
val arbCnt = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b00000001".U(sampleRate.W)) }
arbCnt := Cat( arbCnt(sampleRate-2,0), arbCnt.extract(sampleRate-1) )
val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
@@ -58,29 +37,6 @@ trait CDRInOverSample{ this: CDRInBase =>
val asyncSerDat = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegNext(
Mux1H(
// Seq(
// //(arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 0)) -> sampleReg(3),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 1)) -> sampleReg(0),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 2)) -> sampleReg(1),
// (arbLock === (1.U << 0) & arbCnt === (1.U << 3)) -> sampleReg(2),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 0)) -> sampleReg(2),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 1)) -> sampleReg(3),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 2)) -> sampleReg(0),
// (arbLock === (1.U << 1) & arbCnt === (1.U << 3)) -> sampleReg(1),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 0)) -> sampleReg(1),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 1)) -> sampleReg(2),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 2)) -> sampleReg(3),
// (arbLock === (1.U << 2) & arbCnt === (1.U << 3)) -> sampleReg(0),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 0)) -> sampleReg(0),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 1)) -> sampleReg(1),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 2)) -> sampleReg(2),
// (arbLock === (1.U << 3) & arbCnt === (1.U << 3)) -> sampleReg(3),
// )
(for { i <- 0 until sampleRate; j <- 0 until sampleRate } yield {
//跳变沿到来锁定的位置 锁定拍当前所在的位置 选择锁定拍后一拍的值认为是正确值
((arbLock === (1.U << i)) & (arbCnt === (1.U << j))) -> sampleReg((sampleRate - 1 - i + j) % sampleRate)