diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 4b72c40..61e6bf6 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -482,27 +482,24 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
       (~isUpRecPing & upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 0.U | upSubMsgInfo(0).operator === 2.U)) |
       ( isUpRecPing & upSubMsgInfo(1).devIndex === localDevIndex & (upSubMsgInfo(1).operator === 0.U | upSubMsgInfo(1).operator === 2.U))
-    ) |
-    ((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 0.U | upRecParser.io.subMsgReq.bits.operator === 2.U))
+    )
+    //| ((upRecParser.io.stateNext === STATE_PAYLOAD_DATA) & (upRecParser.io.subMsgReq.bits.devIndex === localDevIndex) & (upRecParser.io.subMsgReq.bits.operator === 0.U | upRecParser.io.subMsgReq.bits.operator === 2.U))
   )
 
   val addrr = Reg(UInt(15.W))  
-  val readSMAddr = Mux1H(Seq(
-    ( upRecParser.io.stateCurr === STATE_SUBMSG_HEADER   ) -> upRecParser.io.subMsgReq.bits.address,
-    ( upRecParser.io.stateCurr === STATE_PAYLOAD_DATA    ) -> addrr,
-  ))
 
+  val isRDReg = addrr(14,11) === "b0000".U
+  val isRDSM1 = addrr(14,11) === "b0010".U
+  val isRDSM3 = addrr(14,11) === "b0100".U
+  val isRDSM5 = addrr(14,11) === "b0110".U
+  val isRDSM7 = addrr(14,11) === "b1000".U
 
-
-  val isRDReg      = (readSMAddr(14,11) === "b0000".U)
-  val isRDSM1      = (readSMAddr(14,11) === "b0010".U)
-  val isRDSM3      = (readSMAddr(14,11) === "b0100".U)
-  val isRDSM5      = (readSMAddr(14,11) === "b0110".U)
-  val isRDSM7      = (readSMAddr(14,11) === "b1000".U)
+  val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) |
+      upRecParser.io.data.fire )
 
   when( upRecParser.io.subMsgReq.fire & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex ){
-    addrr := upRecParser.io.subMsgReq.bits.address + 1.U
-  } .elsewhen( isRead & upRecParser.io.data.fire ){
+    addrr := upRecParser.io.subMsgReq.bits.address
+  } .elsewhen( isLvdsEnR ){
     addrr := addrr + 1.U
   }
 
@@ -535,35 +532,39 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   }
 
-  io.lvds.isEnR   := isRead & isRDReg & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
+
+
+
+    
+  
   io.lvds.addrSel := Mux1H(Seq(
-    isRead  -> readSMAddr(10,0),
+    isRead  -> addrr(10,0),
     isWrite -> addrw(10,0),
   ))
   assert( ~(isRead & isWrite) )
   
 
 
+  io.lvds.isEnR    := isRDReg & isLvdsEnR
+  io.sram_r(0).enr := isRDSM1 & isLvdsEnR
+  io.sram_r(1).enr := isRDSM3 & isLvdsEnR
+  io.sram_r(2).enr := isRDSM5 & isLvdsEnR
+  io.sram_r(3).enr := isRDSM7 & isLvdsEnR
 
-  io.sram_r(0).enr := isRead & isRDSM1 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
-  io.sram_r(1).enr := isRead & isRDSM3 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
-  io.sram_r(2).enr := isRead & isRDSM5 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
-  io.sram_r(3).enr := isRead & isRDSM7 & ( upRecParser.io.subMsgReq.fire | upRecParser.io.data.fire )
-
-  io.sram_r(0).addrr := readSMAddr(10,0)
-  io.sram_r(1).addrr := readSMAddr(10,0)
-  io.sram_r(2).addrr := readSMAddr(10,0)
-  io.sram_r(3).addrr := readSMAddr(10,0)
+  io.sram_r(0).addrr := addrr(10,0)
+  io.sram_r(1).addrr := addrr(10,0)
+  io.sram_r(2).addrr := addrr(10,0)
+  io.sram_r(3).addrr := addrr(10,0)
 
 
   io.dSMenq(0) := isWrite & isWRSM0 & (io.cReg.smTrigLen(0) - 1.U) === addrw(10,0)
-  io.uSMdeq(0) := isRead  & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === readSMAddr(10,0)
+  io.uSMdeq(0) := isRead  & isRDSM1 & (io.cReg.smTrigLen(1) - 1.U) === addrr(10,0)
   io.dSMenq(1) := isWrite & isWRSM2 & (io.cReg.smTrigLen(2) - 1.U) === addrw(10,0)
-  io.uSMdeq(1) := isRead  & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === readSMAddr(10,0)
+  io.uSMdeq(1) := isRead  & isRDSM3 & (io.cReg.smTrigLen(3) - 1.U) === addrr(10,0)
   io.dSMenq(2) := isWrite & isWRSM4 & (io.cReg.smTrigLen(4) - 1.U) === addrw(10,0)
-  io.uSMdeq(2) := isRead  & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === readSMAddr(10,0)
+  io.uSMdeq(2) := isRead  & isRDSM5 & (io.cReg.smTrigLen(5) - 1.U) === addrr(10,0)
   io.dSMenq(3) := isWrite & isWRSM6 & (io.cReg.smTrigLen(6) - 1.U) === addrw(10,0)
-  io.uSMdeq(3) := isRead  & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === readSMAddr(10,0)
+  io.uSMdeq(3) := isRead  & isRDSM7 & (io.cReg.smTrigLen(7) - 1.U) === addrr(10,0)
 
 
 }
diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 0b3b5ac..7945590 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -137,7 +137,7 @@ class SSpiInterface extends SpiInterfaceBase{
       when((byteSel === 1.U || byteSel === 2.U) ){
         exRego := 0.U //地址1，cmd
       } .elsewhen( isSpiRead ){
-        exRego := io.datar
+        exRego := readData
       }
     }.otherwise{
       exRego := exRego << 1
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index 0f7d409..1f4fc7d 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -357,10 +357,7 @@ always @(posedge sck) begin
           exChangeRegi <= 0;
         end
       end else begin
-        if( isQspi ) begin
-          exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
-        end
-
+        exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
       end
     end else begin
       isBusy       <= #5 1'b0;