From 12485fcfff1647b8cebd3d853ee2842c594ee147 Mon Sep 17 00:00:00 2001
From: Ruige Lee <wut.ruigeli@gmail.com>
Date: Wed, 25 Jun 2025 15:25:53 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E4=B8=8A=E8=A1=8C=E5=AD=90?=
 =?UTF-8?q?=E6=8A=A5=E6=96=87=E5=B0=BE=E4=BC=A0=E9=80=92=E9=97=AE=E9=A2=98?=
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---
 .../scala/backBoard/shin/SlaveParser.scala    | 25 ++++++++++++++++---
 .../scala/backBoard/shin/SlaveSendGen.scala   |  1 +
 tb/shinTest/ShinTopSpiTb.v                    |  2 +-
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index d611480..49daa22 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -379,9 +379,28 @@ abstract class SlaveParserBase extends Module{
     }
   }
 
-  when( upSendGen.io.subMsgHeadReq.fire ){ //ready
+  when( upSendGen.io.subMsgTailReq.fire ){
+    when( isUpSendPing ){
+      assert( isUpSubMsgTailValid(0) )
+      isUpSubMsgTailValid(0) := false.B
+    } .otherwise{
+      assert( isUpSubMsgTailValid(1) )
+      isUpSubMsgTailValid(1) := false.B
+    }
+  } .elsewhen( upRecParser.io.subMsgTailReq.fire ){
+    when( isUpRecPing ){
+      assert( ~isUpSubMsgTailValid(0) )
+      isUpSubMsgTailValid(0) := true.B
+    } .otherwise{
+      assert( ~isUpSubMsgTailValid(1) )
+      isUpSubMsgTailValid(1) := true.B
+    }
+  }
+
+
+  when( upSendGen.io.subMsgTailReq.fire ){ //ready
     isUpSendPing := ~isUpSendPing
-  }.elsewhen( upRecParser.io.subMsgHeadReq.fire ){
+  }.elsewhen( upRecParser.io.subMsgTailReq.fire ){
     isUpRecPing := ~isUpRecPing
   }
 
@@ -739,7 +758,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   ))
 
 
-  when( ~isUpRecPing ){ //req fire 后 已经反相
+  when( isUpRecPing ){
     upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(0).io.enq.bits  := 
       Mux( 
diff --git a/src/main/scala/backBoard/shin/SlaveSendGen.scala b/src/main/scala/backBoard/shin/SlaveSendGen.scala
index 5e6a4b6..8e43196 100644
--- a/src/main/scala/backBoard/shin/SlaveSendGen.scala
+++ b/src/main/scala/backBoard/shin/SlaveSendGen.scala
@@ -108,6 +108,7 @@ class SlaveSendGen extends Module{
   io.frameReq.ready := true.B
   io.subMsgHeadReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
   io.subMsgTailReq.ready := stateCurr =/= STATE_SUBMSG_TAIL   & stateNext === STATE_SUBMSG_TAIL
+  assert( ~(io.subMsgTailReq.ready & ~io.subMsgTailReq.valid) )
 
 
   stateNext := Mux1H(Seq(
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index 984677f..d298a25 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -238,7 +238,7 @@ ShinTop s_ShinTop_slv3(
 initial begin
 	clock = 0;
   clk8x = 0;
-	reset = 0;
+	reset = 1;
 
   _reset_deactive = 1'b0;