From 4f2a48e215ec2663a274fd951f9bebcb2b309559 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 21 Jul 2025 14:56:27 +0800 Subject: [PATCH] =?UTF-8?q?=E6=B8=85=E7=A1=AC=E4=BB=B6=E9=94=99=E8=AF=AF?= =?UTF-8?q?=E4=B8=8D=E5=BD=BB=E5=BA=95=EF=BC=8C=E6=94=B9=E7=94=A8reset?= =?UTF-8?q?=E6=B8=85recParser=E7=9A=84=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SlaveParser.scala | 5 ++--- src/main/scala/backBoard/shin/SlaveRecParser.scala | 5 +---- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index df3fd46..f90cd96 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -1047,11 +1047,10 @@ with SlaveParserProbe{ io.intHWTrig(0) := downRecParser.io.isError io.intHWTrig(1) := upRecParser.io.isError - downRecParser.io.resp := io.intHWClr(0) - + downRecParser.reset := reset.asBool | io.intHWClr(0) downSendGen.reset := reset.asBool | io.intHWClr(0) - upRecParser.io.resp := io.intHWClr(1) + upRecParser.reset := reset.asBool | io.intHWClr(1) upSendGen.reset := reset.asBool | io.intHWClr(1) } diff --git a/src/main/scala/backBoard/shin/SlaveRecParser.scala b/src/main/scala/backBoard/shin/SlaveRecParser.scala index 78fbcc9..d8b491a 100644 --- a/src/main/scala/backBoard/shin/SlaveRecParser.scala +++ b/src/main/scala/backBoard/shin/SlaveRecParser.scala @@ -16,7 +16,6 @@ class SlaveRecParserIO extends Bundle{ val subMsgHeadReq = Valid( new SubMsgHeader ) val subMsgTailReq = Valid( new SubMsgTail ) - val resp = Input(Bool()) val isError = Output(Bool()) @@ -34,7 +33,6 @@ class SlaveRecParser extends Module{ val STATE_SUBMSG_TAIL = 4.U val STATE_CRC = 5.U //CRC校验 val STATE_ERROR = 6.U // - val STATE_WAIT = 7.U val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext @@ -204,8 +202,7 @@ class SlaveRecParser extends Module{ ( stateCurr === STATE_CRC ) -> Mux( io.rec.fire & io.rec.bits.tlast, Mux( lengthCnt === (4 - 1).U & isCrcPass, STATE_IDLE, STATE_ERROR ), STATE_CRC ), - ( stateCurr === STATE_ERROR ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ), - ( stateCurr === STATE_WAIT ) -> Mux( io.resp, STATE_IDLE, STATE_WAIT ) + ( stateCurr === STATE_ERROR ) -> STATE_ERROR, ))