From 11f2f701f9584a908dbfc23d0e4c621a7b43d2ea Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Mon, 16 Jun 2025 17:40:55 +0800 Subject: [PATCH] =?UTF-8?q?ebmmu=E5=9C=B0=E5=9D=80=E7=BF=BB=E8=AF=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 4 +- src/main/scala/backBoard/shin/ShinTop.scala | 1 + .../scala/backBoard/shin/SlaveParser.scala | 176 +++++++++++++++--- 3 files changed, 148 insertions(+), 33 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 662e1cb..7cee3a9 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -371,7 +371,7 @@ abstract class InterfaceBase extends Module{ ( 0 until 128 ).map{ i => ( addr === ("h180".U(16.W) + i.U ) ) -> cReg.custom(i) } ++ - ( 0 until 8 ).map{ i => + ( 0 until 8 ).map{ i => Seq( ( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0), ( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8), ( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16), @@ -385,7 +385,7 @@ abstract class InterfaceBase extends Module{ ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op, ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable, - } ++ + )}.reduce(_++_) ++ ( 0 until 8 ).map{ i => ( addr === ("h302".U(16.W) + (i*4).U) ) -> cReg.smTrigLen(i)(7,0) } ++ diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 8796ce8..0476b00 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -329,6 +329,7 @@ trait ShinTopSlave{ this: ShinTopBase => } slaveParser.io.cReg := interface.io.cReg + slaveParser.io.sReg := interface.io.sReg when( interface.io.cReg.modeSel === false.B ){ diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 9113e9d..23c08b1 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -17,6 +17,9 @@ class SubMsgHeader extends Bundle{ val operator = UInt(4.W) //子报文命令类型 val length = UInt(12.W) //子报文负载长度 val workCnt = UInt(16.W) //子报文工作计数 + + def isSeqIndex = style === 0.U + def isLgcIndex = style === 2.U } @@ -65,6 +68,7 @@ class SlaveParserIO extends Bundle{ val isLoop = Output(Bool()) val cReg = Input(new CommonRegisterBundle) + val sReg = Input(new SlaveRegisterBundle) val lvds = new RegAccessInterfaceIO @@ -75,6 +79,8 @@ class SlaveParserIO extends Bundle{ abstract class SlaveParserBase extends Module{ val io: SlaveParserIO = IO(new SlaveParserIO) + val sReg = io.sReg + val FRAME_STYLE_COMMON = 0.U @@ -376,6 +382,16 @@ trait SlaveParserIndex{ this: SlaveParserBase => trait SlaveParserRW{ this: SlaveParserBase => + // val isSeqIndexMatch = + // (downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex) + + // val downLgcAddress = Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) + // val isLgcIndexMatch = + // (downRecParser.io.subMsgReq.bits.isLgcIndex & + + + + //下行接收 when( downRecParser.io.subMsgReq.fire ){ when( isDownRecPing ){ @@ -403,32 +419,84 @@ trait SlaveParserRW{ this: SlaveParserBase => //写入 SM或寄存器空间 val addrw = Reg(UInt(15.W)) + val logicAddrwNext = Wire( UInt(30.W) ) + val logicAddrw = RegNext(logicAddrwNext) val isWRReg = (addrw(14,11) === "b0000".U) - val isWRSM0 = (addrw(14,11) === "b0001".U) - val isWRSM2 = (addrw(14,11) === "b0011".U) - val isWRSM4 = (addrw(14,11) === "b0101".U) - val isWRSM6 = (addrw(14,11) === "b0111".U) + val isWRSM0 = (addrw(14,11) === "b0001".U) + val isWRSM2 = (addrw(14,11) === "b0011".U) + val isWRSM4 = (addrw(14,11) === "b0101".U) + val isWRSM6 = (addrw(14,11) === "b0111".U) val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相 - ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(0).devIndex === localDevIndex)) | - ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & (downSubMsgInfo(1).devIndex === localDevIndex)) | + ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || downSubMsgInfo(0).isLgcIndex) ) | + ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || downSubMsgInfo(1).isLgcIndex) ) | ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) | ( isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) ) ) ) - when( downRecParser.io.subMsgReq.fire & ( - downRecParser.io.subMsgReq.bits.devIndex === localDevIndex | - downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | - downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR - ) - ){ - addrw := downRecParser.io.subMsgReq.bits.address - } .elsewhen( isWrite & downRecParser.io.data.fire ){ - addrw := addrw + 1.U + val downTransLenCnt = RegInit(0.U) + + val isDownLgcAddrwAcquireTrans = //是否触发地址转换 + (downTransLenCnt === 0.U) & ( (0 until 8).map{ i => + sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr) + }.reduce(_|_)) + + val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).pAddr + } + ) + + val acquireDownTransLen = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).length + } + ) + + when( isDownLgcAddrwAcquireTrans ){ //装填计数器 + downTransLenCnt := acquireDownTransLen + } .elsewhen( downRecParser.io.data.fire & downTransLenCnt =/= 0.U){ + downTransLenCnt := downTransLenCnt - 1.U } + //组合逻辑 + when( downRecParser.io.subMsgReq.fire & ( + (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex + )){//组合逻辑 + logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address ) + } .elsewhen( isWrite & downRecParser.io.data.fire ){//组合逻辑 + logicAddrwNext := logicAddrw + 1.U + } .otherwise{//组合逻辑 + logicAddrwNext := logicAddrw + } + + + when( downRecParser.io.subMsgReq.fire ){ //子包头装填 + when( + ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ){ //常规寻址 + addrw := downRecParser.io.subMsgReq.bits.address + } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ //逻辑寻址 + addrw := acquireDownPhyAddrw + } + } .elsewhen( isWrite & downRecParser.io.data.fire ){ + when( + ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) | + ( downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR ) + ){ + addrw := addrw + 1.U + } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ + addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U ) + } + } + + + io.lvds.isEnW := isWrite & isWRReg & downRecParser.io.data.fire io.lvds.dataw := downRecParser.io.data.bits @@ -453,10 +521,6 @@ trait SlaveParserRW{ this: SlaveParserBase => - // val SUBMSG_OPERATOR_BOARDREAD = "hd".U - // val SUBMSG_OPERATOR_BOARDWRITE = "he".U - // val SUBMSG_OPERATOR_BOARDRDWR = "hf".U - //上行接收 when( upRecParser.io.subMsgReq.fire ){ @@ -487,14 +551,55 @@ trait SlaveParserRW{ this: SlaveParserBase => //读出uSM val isRead = ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( - (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex) | - ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex) | + (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || upSubMsgInfo(0).isLgcIndex)) | + ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || upSubMsgInfo(1).isLgcIndex)) | (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) | ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) ) ) val addrr = Reg(UInt(15.W)) + val logicAddrrNext = Wire( UInt(30.W) ) + val logicAddrr = RegNext(logicAddrrNext) + + val upTransLenCnt = RegInit(0.U) + + val isUpLgcAddrwAcquireTrans = //是否触发地址转换 + (upTransLenCnt === 0.U) & ( (0 until 8).map{ i => + sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr) + }.reduce(_|_)) + + val acquireUpPhyAddrw = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).pAddr + } + ) + + val acquireUpTransLen = Mux1H( //选择一个ebmmu + (0 until 8).map{ i => + (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) -> + sReg.ebmmu(i).length + } + ) + + when( isUpLgcAddrwAcquireTrans ){ //装填计数器 + upTransLenCnt := acquireUpTransLen + } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){ + upTransLenCnt := upTransLenCnt - 1.U + } + + //组合逻辑 + when( upRecParser.io.subMsgReq.fire & ( + (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex + )){//组合逻辑 + logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address ) + } .elsewhen( isRead & upRecParser.io.data.fire ){//组合逻辑 + logicAddrrNext := logicAddrw + 1.U + } .otherwise{//组合逻辑 + logicAddrrNext := logicAddrr + } + val isRDReg = addrr(14,11) === "b0000".U val isRDSM1 = addrr(14,11) === "b0010".U @@ -505,15 +610,24 @@ trait SlaveParserRW{ this: SlaveParserBase => val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) | upRecParser.io.data.fire ) - when( upRecParser.io.subMsgReq.fire & ( - upRecParser.io.subMsgReq.bits.devIndex === localDevIndex | - upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | - upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR - ) - ){ - addrr := upRecParser.io.subMsgReq.bits.address + when( upRecParser.io.subMsgReq.fire){ + when( + ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + ){ + addrr := upRecParser.io.subMsgReq.bits.address + } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + addrr := acquireUpPhyAddrw + } } .elsewhen( isLvdsEnR ){ - addrr := addrr + 1.U + when( + ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) | + ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR) + ){ + addrr := addrr + 1.U + } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){ + addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrwAcquireTrans, acquireUpPhyAddrw, 0.U), addrr + 1.U ) + } } val upStreamData = Mux1H(Seq( @@ -529,7 +643,7 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(0).io.enq.valid := upRecParser.io.data.valid upRecFifo(0).io.enq.bits := Mux( - ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(0).devIndex === localDevIndex, upStreamData, + ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | upSubMsgInfo(0).isLgcIndex), upStreamData, Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits ) ) @@ -544,7 +658,7 @@ trait SlaveParserRW{ this: SlaveParserBase => upRecFifo(1).io.enq.valid := upRecParser.io.data.valid upRecFifo(1).io.enq.bits := Mux( - ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & upSubMsgInfo(1).devIndex === localDevIndex, upStreamData, + ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | upSubMsgInfo(1).isLgcIndex), upStreamData, Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits, upRecParser.io.data.bits )