滤波 表决 鉴相同时存在

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -90,13 +90,74 @@ trait CDRInMultiSample{ this: CDRInBase =>
   }
 
 
-  val asyncSerDat = PopCount(sampleReg_sync) >= 12.U
+// val flitReg =
+//   for( i <- 1 until 22 ) yield {
+//     (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+//     (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+//     (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+//   }
 
 
-    // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
+
+  // val asyncSerDat = PopCount(flitReg) >= 11.U
 
 
-  syncSerDat := ShiftRegister( asyncSerDat, 2 )
+val flitReg =
+  for( i <- 6 until 22 ) yield {
+    (sampleReg_sync(i-1) & sampleReg_sync(i+0)) |
+    (sampleReg_sync(i-1) & sampleReg_sync(i+1)) |
+    (sampleReg_sync(i+0) & sampleReg_sync(i+1))
+  }
+
+
+val arbLock = Reg(UInt( 16.W ))
+
+  //优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的
+  when( flitReg(0) ^ flitReg(1) ){
+    arbLock := "b1".U(16.W) << 7
+  } .elsewhen( flitReg(1) ^ flitReg(2) ){
+    arbLock := "b1".U(16.W) << 8
+  } .elsewhen( flitReg(2) ^ flitReg(3) ){
+    arbLock := "b1".U(16.W) << 9
+  } .elsewhen( flitReg(3) ^ flitReg(4) ){
+    arbLock := "b1".U(16.W) << 10
+  } .elsewhen( flitReg(4) ^ flitReg(5) ){
+    arbLock := "b1".U(16.W) << 11
+  } .elsewhen( flitReg(5) ^ flitReg(6) ){
+    arbLock := "b1".U(16.W) << 12
+  } .elsewhen( flitReg(6) ^ flitReg(7) ){
+    arbLock := "b1".U(16.W) << 13
+  } .elsewhen( flitReg(7) ^ flitReg(8) ){
+    arbLock := "b1".U(16.W) << 14
+  } .elsewhen( flitReg(8) ^ flitReg(9) ){
+    arbLock := "b1".U(16.W) << 15
+  } .elsewhen( flitReg(9) ^ flitReg(10) ){
+    arbLock := "b1".U(16.W) << 0
+  } .elsewhen( flitReg(10) ^ flitReg(11) ){
+    arbLock := "b1".U(16.W) << 1
+  } .elsewhen( flitReg(11) ^ flitReg(12) ){
+    arbLock := "b1".U(16.W) << 2
+  } .elsewhen( flitReg(12) ^ flitReg(13) ){
+    arbLock := "b1".U(16.W) << 3
+  } .elsewhen( flitReg(13) ^ flitReg(14) ){
+    arbLock := "b1".U(16.W) << 4
+  } .elsewhen( flitReg(14) ^ flitReg(15) ){
+    arbLock := "b1".U(16.W) << 5
+  } .elsewhen( flitReg(15) ^ flitReg(0) ){
+    arbLock := "b1".U(16.W) << 6
+  } 
+
+  val asyncSerDat = 
+    Mux1H(
+      (for { i <- 0 until clkNum } yield {
+        (arbLock === (1.U << i)) -> flitReg(i)
+      })
+    )
+
+
+
+
+  syncSerDat := asyncSerDat //ShiftRegister( asyncSerDat, 2 )
 
 
   testIO := Cat( syncSerDat, asyncSerDat, io.serDat )