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Revert "最后几个比特锁不住"

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This reverts commit 97211f0962.
This commit is contained in:
RuigeLee
2024-09-23 17:40:35 +08:00
parent 97211f0962
commit 10b2e4c78f
1 changed files with 5 additions and 13 deletions
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18
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -95,12 +95,10 @@ trait CDRInAxis{ this: CDRInBase =>
val operation = header(15,8)
val param = header( 7,0)
val isArbLock: Bool
val isPrebleLock = RegInit(false.B)
stateNext :=
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( isPrebleLock & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_IDLE) -> ( Mux( isArbLock & (shiftData === ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U) ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD )), // PAYLOAD
(stateCurr === STATE_CRC) -> ( Mux( (byteCnt === 3.U) & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
@@ -108,21 +106,15 @@ trait CDRInAxis{ this: CDRInBase =>
val isArbLock: Bool
when( shiftData === ETH_PRE & stateCurr === STATE_IDLE & isArbLock ){
isPrebleLock := true.B
} .elsewhen( (shiftData =/= "h55".U & shiftData =/= "haa".U) | ~isArbLock ){
isPrebleLock := false.B
}
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isPrebleLock ){ //first align
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock ){ //first align
bitCnt := 0.U
} .otherwise{
bitCnt := bitCnt + 1.U
}
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isPrebleLock ){ //first align
when( shiftData === ETH_SFD & stateCurr === STATE_IDLE & isArbLock ){ //first align
byteCnt := 0.U
} .elsewhen( bitCnt === 7.U ){
when( stateCurr === STATE_HEADER ){