diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 222c451..1f3a0f1 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
 
   //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
-  val multiCLK = IO(Input(Vec(4, Bool())))
+  val multiCLK = IO(Input(Vec(16, Bool())))
 
 
-  val sampleReg = Wire(Vec(5, Bool()))
+  val sampleReg = Wire(Vec(23, Bool()))
   
-  for( i <- 0 until 4 ) {
+  for( i <- 0 until 16 ) {
     sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
   }
-  for( i <- 4 until 5 ){
-    sampleReg(i) := withClockAndReset(multiCLK(i-1).asClock, reset.asBool){ RegNext(sampleReg(i-1))}
+  for( i <- 16 until 23 ){
+    sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))}
   }
 
 
 
-  val asyncSerDat = PopCount(sampleReg) >= 3.U
+  val asyncSerDat = PopCount(sampleReg) >= 12.U
 
 
     // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index d5513d4..45638a1 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
   val uDatIn   = Input(Bool())
   val uDatOut  = Output(Bool())
 
-  val multiCLK = Input(Vec(4, Bool()))
+  val multiCLK = Input(Vec(16, Bool()))
 
   val iqspi = new QSPIInterfaceIO
   val ospi = new SSPIInterfaceIO