pass tx rx status ctrl
This commit is contained in:
RuigeLee
@@ -67,7 +67,7 @@ abstract class MacTxBase extends Module{
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val UnderRun = Wire(Bool())
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val TooBig = Wire(Bool())
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val Crc = Wire(UInt(32.W))
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val CrcError = Wire(Bool())
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@@ -99,7 +99,7 @@ abstract class MacTxBase extends Module{
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val NibCntEq7 = NibCnt === 7.U
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val NibCntEq15 = NibCnt === 15.U
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val RetryCnt = RegInit(0.U(4.W))
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val RetryCnt = RegInit(0.U(4.W)); io.RetryCnt := RetryCnt
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}
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@@ -107,7 +107,7 @@ abstract class MacTxBase extends Module{
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trait MacTxFSM { this: MacTxBase =>
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// Defining the next state
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io.StartIPG := StateDefer & ~ExcessiveDefer & ~io.CarrierSense
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StartIPG := StateDefer & ~ExcessiveDefer & ~io.CarrierSense
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val StartIdle = StateIPG & (Rule1 & NibCnt(6,0) >= io.IPGT | ~Rule1 & NibCnt(6,0) >= io.IPGR2)
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@@ -118,26 +118,29 @@ trait MacTxFSM { this: MacTxBase =>
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val StartPAD = ~io.Collision & StateData(1) & io.TxEndFrm & io.Pad & ~NibbleMinFl
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val StartFCS = ~io.Collision & StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & io.CrcEn
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| ~io.Collision & StatePAD & NibbleMinFl & io.CrcEn
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StartFCS :=
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(~io.Collision & StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & io.CrcEn) |
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(~io.Collision & StatePAD & NibbleMinFl & io.CrcEn)
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StartJam := (io.Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (StateData(1) | StateData(0)) | StatePAD | StateFCS)
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StartBackoff := StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~io.NoBckof
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StartDefer := StateIPG & ~Rule1 & io.CarrierSense & NibCnt(6,0) <= io.IPGR1 & NibCnt(6,0) =/= io.IPGR2
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| StateIdle & io.CarrierSense
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| StateJam & NibCntEq7 & (io.NoBckof | RandomEq0 | ~ColWindow | RetryMax)
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| StateBackOff & (io.TxUnderRun | RandomEqByteCnt)
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| io.StartTxDone | TooBig;
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StartDefer :=
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(StateIPG & ~Rule1 & io.CarrierSense & NibCnt(6,0) <= io.IPGR1 & NibCnt(6,0) =/= io.IPGR2) |
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(StateIdle & io.CarrierSense) |
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(StateJam & NibCntEq7 & (io.NoBckof | RandomEq0 | ~ColWindow | RetryMax)) |
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(StateBackOff & (io.TxUnderRun | RandomEqByteCnt)) |
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io.StartTxDone |
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TooBig
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io.DeferIndication := StateIdle & io.CarrierSense;
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io.DeferIndication := StateIdle & io.CarrierSense
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when(StartDefer | StartIdle){
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StateIPG := false.B
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}.elsewhen(io.StartIPG){
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}.elsewhen(StartIPG){
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StateIPG := true.B
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}
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@@ -177,7 +180,7 @@ trait MacTxFSM { this: MacTxBase =>
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StateBackOff := true.B
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}
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when(io.StartIPG){
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when(StartIPG){
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StateDefer := false.B
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} .elsewhen(StartDefer){
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StateDefer := true.B
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@@ -208,7 +211,7 @@ trait MacTxCounter { this: MacTxBase =>
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(StateDefer & ExcessiveDefer & ~io.TxStartFrm) |
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(StatePreamble & NibCntEq15) |
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(StateJam & NibCntEq7) |
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StateIdle | StartDefer | io.StartIPG | StartFCS | StartJam
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StateIdle | StartDefer | StartIPG | StartFCS | StartJam
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when(ResetNibCnt){
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@@ -217,7 +220,7 @@ trait MacTxCounter { this: MacTxBase =>
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NibCnt := NibCnt + 1.U
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}
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NibbleMinFl := NibCnt >= (((MinFL-4.U)<<1) - 1.U) // FCS should not be included in NibbleMinFl
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NibbleMinFl := NibCnt >= (((io.MinFL-4.U)<<1) - 1.U) // FCS should not be included in NibbleMinFl
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ExcessiveDefer := NibCnt(13,0) === "h17b7".U & ~io.ExDfrEn; // 6071 nibbles
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@@ -258,10 +261,12 @@ trait MacTxCRC{ this: MacTxBase =>
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val Data_Crc =
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Mux1H(Seq(
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StateData(0) -> Cat( TxData(3), TxData(2), TxData(1), TxData(0) ),
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StateData(1) -> Cat( TxData(7), TxData(6), TxData(5), TxData(4) ),
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StateData(0) -> Cat( io.TxData(0), io.TxData(1), io.TxData(2), io.TxData(3) ),
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StateData(1) -> Cat( io.TxData(4), io.TxData(5), io.TxData(6), io.TxData(7) ),
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))
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val Crc = RegInit("hFFFFFFFF".U(32.W))
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when( Initialize_Crc ){
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Crc := "hFFFFFFFF".U
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} .otherwise{
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@@ -337,25 +342,25 @@ trait MacTxRandom{ this: MacTxBase =>
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}
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class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with MacTxRandom{
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val MTxD = RegInit(UInt(4.W)); io.MTxD := MTxD
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val MTxD = RegInit(0.U(4.W)); io.MTxD := MTxD
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val StopExcessiveDeferOccured = RegInit(false.B)
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val StatusLatch = RegInit(false.B)
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val TxUsedData = RegNext(StartData.orR, false.B)
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val TxDone = RegInit(false.B)
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val TxRetry = RegInit(false.B)
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val TxAbort = RegInit(false.B)
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val TxUsedData = RegNext(StartData(0) | StartData(1), false.B); io.TxUsedData := TxUsedData
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val TxDone = RegInit(false.B); io.TxDone := TxDone
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val TxRetry = RegInit(false.B); io.TxRetry := TxRetry
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val TxAbort = RegInit(false.B); io.TxAbort := TxAbort
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val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn
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val MTxErr = RegNext( TooBig | UnderRun, false.B) // Transmit error
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val MTxErr = RegNext( TooBig | UnderRun, false.B); io.MTxErr := MTxErr// Transmit error
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val WillTransmit = RegNext(StartPreamble | StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B) // WillTransmit
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val WillTransmit = RegNext(StartPreamble | StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.WillTransmit := WillTransmit// WillTransmit
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io.ResetCollision := ~(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS)
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val ExcessiveDeferOccured = io.TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured
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io.StartTxDone = ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & ~io.CrcEn)
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io.StartTxDone := ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & ~io.CrcEn)
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UnderRun := StateData(0) & io.TxUnderRun & ~io.Collision
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TooBig := ~io.Collision & MaxFrame & (StateData(0) & ~io.TxUnderRun | StateFCS);
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val StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
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@@ -424,8 +429,8 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with
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when( true.B ){
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MTxD := // Transmit nibble
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Mux(
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StateData(0), TxData(3,0), // Lower nibble
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Mux(StateData(1), TxData(7,4), // Higher nibble
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StateData(0), io.TxData(3,0), // Lower nibble
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Mux(StateData(1), io.TxData(7,4), // Higher nibble
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Mux( StateFCS, Cat(~Crc.extract(28), ~Crc.extract(29), ~Crc.extract(30), ~Crc.extract(31)), // Crc
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Mux(StateJam, 9.U, // Jam pattern
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Mux(
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