diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index ca8d1f5..f414a15 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -69,22 +69,28 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown } trait BackBoardSlvStatusLed { this: BackBoardSlvLocal => - val flashCounter = RegInit( 0.U( 17.W ) ) + val flashCounter = RegInit( 0.U( 16.W ) ) + val flash2HZ = Reg(Bool()) + val flash1HZ = Reg(Bool()) + when( us10Trigger ){ - when( flashCounter >= 100000.U ){ + when( flashCounter >= 50000.U ){ flashCounter := 0.U + flash2HZ := ~flash2HZ + when( flash2HZ ){ + flash1HZ := ~flash1HZ + } } .otherwise{ flashCounter := flashCounter + 1.U } } - val flash1HZ = flashCounter.extract(16) - val flash2HZ = flashCounter.extract(15) + val LED_PR = IO(Output( Bool() )) - LED_PR := Mux1H(Seq( + LED_PR := ~Mux1H(Seq( ( statusLed === "b00".U ) -> flash2HZ, ( statusLed === "b01".U ) -> flash1HZ, ( statusLed === "b10".U ) -> true.B, @@ -112,15 +118,15 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal => val in = IO(Input(UInt((8*gp).W))) - val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U(5.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) )) + val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) )) val flitTrigger = Wire(Vec(9, Bool())) flitTrigger(0) := true.B - flitTrigger(1) := flitCnt(1) === 24.U - when( ~RegNext(us10Trigger) & us10Trigger ){ - flitCnt(1) := Mux( flitCnt(1) >= 24.U, 0.U, flitCnt(1) + 1.U ) - } + flitTrigger(1) := us10Trigger + // when( ~RegNext(us10Trigger) & us10Trigger ){ + // flitCnt(1) := Mux( flitCnt(1) >= 24.U, 0.U, flitCnt(1) + 1.U ) + // } flitTrigger(2) := flitCnt(2) === 1.U when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){