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增加plic文件，测试仿真

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This commit is contained in:
bacon
2025-02-10 23:59:35 +08:00
parent be04224806
commit 0dc8c40076
8 changed files with 159 additions and 84 deletions
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16
tb/sw/src/MstMain.c
View File

@@ -3,22 +3,12 @@
#include "system_cfg.h"
#include "sysDef.h"
#include "halfLvdsMacSvr.h"
#include "plic.h"
#ifdef __riscv_i
#define USING_POLL_STRATEGY
#endif
//-------------------------------------------------------------------
volatile uint32_t *const plic_priority = (uint32_t *)(0xc000000U);
volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
volatile uint32_t *plic_threshold_0 = (uint32_t*)( 0xc000000U + 0X200000 );
volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
//-------------------------------------------------------------------
//internal function
static uint32_t init_plic(void);
@@ -64,11 +54,11 @@ uint32_t init_plic(void)
//| 1 << CDR_INT_RX0END
| 1 << CDR_INT_RX1END
| 1 << CDR_INT_TX0_FIFO_DEQ
//| 1 << CDR_INT_TX0_FIFO_DEQ
//| 1 << CDR_INT_TX1_FIFO_DEQ
//| 1 << CDR_INT_RX0_FIFO_ENQ
| 1 << CDR_INT_RX1_FIFO_ENQ
//| 1 << CDR_INT_RX1_FIFO_ENQ
;
plic_priority[CDR_INT_TX0END] = 1;

11
tb/sw/src/SlvMain.c
View File

@@ -6,18 +6,13 @@
#include "system_cfg.h"
#include "halfLvdsMacSvr.h"
#include "sysDef.h"
#include "plic.h"
#ifdef __riscv_i
#define USING_POLL_STRATEGY
#endif
volatile uint32_t *const plic_priority = (uint32_t *)(0xc000000U);
volatile uint32_t *plic_pending_0_31 = (uint32_t*)( 0xc000000U + 0X001000 );
volatile uint32_t *plic_enable_0_31 = (uint32_t*)( 0xc000000U + 0X002000 );
volatile uint32_t *plic_threshold_0 = (uint32_t*)( 0xc000000U + 0X200000 );
volatile uint32_t *plic_claim = (uint32_t*)( 0xc000000U + 0X200004 );
static void error();
static uint32_t init_plic(void);
@@ -76,8 +71,8 @@ uint32_t init_plic(void)
//| 1 << CDR_INT_TX0_FIFO_DEQ
//| 1 << CDR_INT_TX1_FIFO_DEQ
| 1 << CDR_INT_RX0_FIFO_ENQ
| 1 << CDR_INT_RX1_FIFO_ENQ
//| 1 << CDR_INT_RX0_FIFO_ENQ
//| 1 << CDR_INT_RX1_FIFO_ENQ
;
plic_priority[CDR_INT_TX0END] = 1;

126
tb/sw/src/halfLvdsMacSvr.c
View File

@@ -2,6 +2,7 @@
#include "sysDef.h"
#include "tl2cdr.h"
#include "halfLvdsMacSvr.h"
#include "plic.h"
//-------------------------------------------------------------------
uint8_t MST_TX_BUF[TX_BUF_NUM * TX_BUF_MAX_LEN] __attribute__((aligned(32)));
@@ -76,110 +77,135 @@ uint32_t HLM_poll(uint32_t mode)
{
if (mode == WORKMODE_MASTER)
{
uint32_t pkt_len = 32;
uint32_t tx_pkt_len = 128;
uint32_t rx_pkt_len = 0;
uint32_t rx_start = 0;
uint32_t status;
uint32_t i;
uint32_t *data_ptr = (uint32_t *)MST_TX_BUF;
uint32_t *tx_data_ptr = (uint32_t *)MST_TX_BUF;
uint32_t *rx_data_ptr = (uint32_t *)MST_RX_BUF;
//准备数据
for (i = 0; i < pkt_len; i++)
for (i = 0; i < tx_pkt_len; i++)
MST_TX_BUF[i] = i;
//开始发送工作
*tx0_txLen = pkt_len + 8;
*tx0_txFifo = (pkt_len << 20) | (0 << 16) | 0;
*tx0_txLen = tx_pkt_len + 8;
*tx0_txFifo = (tx_pkt_len << 20) | (0 << 16) | 0;
uint32_t tx_index = 0;
uint32_t rx_index = 0;
for (i = 0; i < HLM_TX_FIFO_LEN - 1; i++)
{
if ((tx_index * 4) < tx_pkt_len)
{
*tx0_txFifo = tx_data_ptr[tx_index];
tx_index++;
}
else
break;
}
while (1)
{
if (isr_flag[CDR_INT_TX0_FIFO_DEQ])
status = *HLM_status;
if (((tx_index * 4) < tx_pkt_len) && (status & HLM_TX0_FIFO_FULL))
{
isr_flag[CDR_INT_TX0_FIFO_DEQ] = 0;
if (tx_index < pkt_len / 4)
*tx0_txFifo = tx_data_ptr[tx_index];
tx_index++;
}
if ((rx_start) && (status & HLM_RX1_VALID))
{
rx_data_ptr[rx_index] = *rx1_rxFifo;
if (rx_index == 0)
rx_pkt_len = (rx_data_ptr[rx_index] >> 20) + 4;
rx_index++;
if (rx_pkt_len <= (rx_index * 4))
{
*tx0_txFifo = data_ptr[tx_index];
tx_index++;
rx_start = 0;
*rx0_softReset = 1;
*tx1_softReset = 1;
}
}
if (isr_flag[CDR_INT_RX1START])
{
isr_flag[CDR_INT_RX1START] = 0;
MST_RX_BUF[rx_index] = *rx1_rxFifo;
rx_index++;
rx_start = 1;
rx_index = 0;
}
#if 0
if (isr_flag[CDR_INT_RX1_FIFO_ENQ])
{
isr_flag[CDR_INT_RX1_FIFO_ENQ] = 0;
MST_RX_BUF[rx_index] = *rx1_rxFifo;
rx_index++;
}
if (isr_flag[CDR_INT_RX1END])
break;
#endif
}
}
else if (mode == WORKMODE_SLAVE)
{
uint32_t rx_index = 0;
uint32_t rx_len;
uint32_t tx_pkt_len;
uint32_t rx_pkt_len = 0;
uint32_t rx_start = 0;
uint32_t status;
while (1)
{
if (isr_flag[CDR_INT_TX0_FIFO_DEQ])
//status = *HLM_status;
if (rx_start) // && (status & HLM_RX0_VALID))
{
isr_flag[CDR_INT_TX0_FIFO_DEQ] = 0;
uint32_t data;
data = *rx0_rxFifo;
if (rx_index == 0)
{
rx_pkt_len = (data >> 20) + 4;
*tx1_txLen = rx_pkt_len + 4;
}
rx_index++;
*tx1_txFifo = data;
if (rx_pkt_len <= (rx_index * 4))
{
rx_start = 0;
}
}
//tx1 上行
if (isr_flag[CDR_INT_TX1_FIFO_DEQ])
{
isr_flag[CDR_INT_TX1_FIFO_DEQ] = 0;
}
//rx0 下行
//rx0 下行
if (isr_flag[CDR_INT_RX0START])
{
isr_flag[CDR_INT_RX0START] = 0;
rx_start = 1;
}
if (isr_flag[CDR_INT_RX0_FIFO_ENQ])
//rx1 上行
if (isr_flag[CDR_INT_RX1START])
{
isr_flag[CDR_INT_RX0_FIFO_ENQ] = 0;
if (rx_index == 0)
{
uint32_t first = *rx0_rxFifo;
uint32_t len;
len = (first >> 20U);
*tx1_txLen = len + 8U;
*tx1_txFifo = first;
rx_len = len + 4;
rx_index += 4U;
}
else
{
if (rx_len > rx_index)
{
*tx1_txFifo = *rx0_rxFifo;
rx_index += 4U;
}
}
isr_flag[CDR_INT_RX1START] = 0;
}
if (isr_flag[CDR_INT_RX0END])
{
isr_flag[CDR_INT_RX0END] = 0;
break;
//break;
}
if (isr_flag[CDR_INT_RX1END])
{
isr_flag[CDR_INT_RX1END] = 0;
break;
//break;
}
}
}

9
tb/sw/src/plic.c Normal file
View File

@@ -0,0 +1,9 @@
#include "plic.h"
volatile uint32_t *const plic_priority = (uint32_t *)(PLIC_BASE);
volatile uint32_t *const plic_pending_0_31 = (uint32_t*)( PLIC_BASE + PLIC_PENDING_0_31 );
volatile uint32_t *const plic_enable_0_31 = (uint32_t*)( PLIC_BASE + PLIC_ENABLE_0_31 );
volatile uint32_t *const plic_threshold_0 = (uint32_t*)( PLIC_BASE + PLIC_THRESHOLD_0 );
volatile uint32_t *const plic_claim = (uint32_t*)( PLIC_BASE + PLIC_CLAIM );

39
tb/sw/src/plic.h Normal file
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@@ -0,0 +1,39 @@
#ifndef __PLIC_H__
#define __PLIC_H__
#define PLIC_BASE (0xc000000U)
#define PLIC_PRIORITY (0U)
#define PLIC_PENDING_0_31 (0X001000U)
#define PLIC_ENABLE_0_31 (0X002000U)
#define PLIC_THRESHOLD_0 (0X200000U)
#define PLIC_CLAIM (0X200004U)
#define CDR_INT_TX0END 14U
#define CDR_INT_TX1END 15U
#define CDR_INT_RX0ERROR 16U
#define CDR_INT_RX1ERROR 17U
#define CDR_INT_RX0START 18U
#define CDR_INT_RX1START 19U
#define CDR_INT_RX0END 20U
#define CDR_INT_RX1END 21U
#define CDR_INT_TX0_FIFO_DEQ 22U
#define CDR_INT_TX1_FIFO_DEQ 23U
#define CDR_INT_RX0_FIFO_ENQ 24U
#define CDR_INT_RX1_FIFO_ENQ 25U
#ifndef __ASSEMBLER__
#include "stdint.h"
extern volatile uint32_t *const plic_priority;
extern volatile uint32_t *const plic_pending_0_31;
extern volatile uint32_t *const plic_enable_0_31;
extern volatile uint32_t *const plic_threshold_0;
extern volatile uint32_t *const plic_claim;
#endif
#endif

2
tb/sw/src/sysDef.h
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@@ -9,5 +9,7 @@
#define WORKMODE_MASTER 0
#define WORKMODE_SLAVE 1
#endif

26
tb/sw/tl2cdr/tl2cdr.h
View File

@@ -7,19 +7,6 @@
#define TL2CDR_BASE 0x10000000U
#define CDR_INT_TX0END 14U
#define CDR_INT_TX1END 15U
#define CDR_INT_RX0ERROR 16U
#define CDR_INT_RX1ERROR 17U
#define CDR_INT_RX0START 18U
#define CDR_INT_RX1START 19U
#define CDR_INT_RX0END 20U
#define CDR_INT_RX1END 21U
#define CDR_INT_TX0_FIFO_DEQ 22U
#define CDR_INT_TX1_FIFO_DEQ 23U
#define CDR_INT_RX0_FIFO_ENQ 24U
#define CDR_INT_RX1_FIFO_ENQ 25U
#define TX0_WriteSoftReset 0x00U
#define TX0_WriteTxLen 0x04U
#define TX0_WriteTxFifo 0x08U
@@ -48,6 +35,19 @@
#define HLM_ReadIsLast 0x5CU
#define HLM_TX_FIFO_LEN 16U
#define HLM_RX_FIFO_LEN 16U
#define HLM_TX0_FIFO_FULL (1U<<0U)
#define HLM_TX1_FIFO_FULL (1U<<1U)
#define HLM_TX0_BUSY (1U<<2U)
#define HLM_TX1_BUSY (1U<<3U)
#define HLM_RX0_ERROR (1U<<4U)
#define HLM_RX1_ERROR (1U<<5U)
#define HLM_RX0_VALID (1U<<6U)
#define HLM_RX1_VALID (1U<<7U)
#ifndef __ASSEMBLER__
extern volatile uint32_t * const tx0_softReset;
extern volatile uint32_t * const tx0_txLen;