tlast以fifo为空判定，而不是txlen

2024-10-28 10:37:57 +08:00
parent d8361401b5
commit 0ce1a08586
1 changed files with 2 additions and 2 deletions
--- a/src/main/scala/backBoard/pico/TLCDR.scala
+++ b/src/main/scala/backBoard/pico/TLCDR.scala
@@ -71,7 +71,7 @@ trait TLCDRTx{ this: TLCDRBase =>
    (txCnt === 3.U) -> txData(31, 24),
  ))

-  CDROut.io.axis.bits.tlast := txLen === 0.U & ~txFifo.io.deq.valid & txCnt === 3.U
+  CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
  CDROut.io.axis.bits.tuser := isTxError
  CDROut.io.axis.valid := isTxBusy