整理测试用例

This commit is contained in:
2025-09-06 15:51:04 +08:00
parent d9da8fe7db
commit 0c76190720
4 changed files with 1198 additions and 79 deletions

View File

@@ -36,12 +36,10 @@ module ShinTopSpiTb(
reg clock; reg clock;
reg reset; reg reset;
reg clk8x;
reg [15:0] multiCLK; reg [15:0] multiCLK;
reg clock2;
reg [15:0] multiCLK2;
`include "dev_predef.vh" `include "dev_predef.vh"
@@ -385,7 +383,7 @@ ShinTop s_ShinTop_slv3(
initial begin initial begin
clock = 0; clock = 0;
clock2 = 0; clk8x = 0;
reset = 1; reset = 1;
latch0 = 0; latch0 = 0;
@@ -397,15 +395,15 @@ initial begin
spi_csn = {`SPI_CSN_NUM{1'b1}}; //~15'b0; spi_csn = {`SPI_CSN_NUM{1'b1}}; //~15'b0;
#10000000 #100
reset <= 1; reset <= 1;
#24000000 #240
reset <= 0; reset <= 0;
#8000000000000 //#20000000
#8000000000000 #1000000000
#8000000000000 //#5000000
$display("Time Out !!!"); $display("Time Out !!!");
$fclose(spidata_file); $fclose(spidata_file);
@@ -413,7 +411,11 @@ initial begin
end end
initial begin initial begin
forever begin #8000000 clock <= ~clock; end forever begin #20 clk8x <= ~clk8x; end
end
initial begin
forever begin #80 clock <= ~clock; end
end end
@@ -422,47 +424,10 @@ generate
initial begin initial begin
multiCLK[i] = 0; multiCLK[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin for( integer j = 0; j < i; j = j + 1 ) begin
#1000000 #10
; ;
end end
forever begin #8000000 multiCLK[i] <= ~multiCLK[i]; end forever begin #80 multiCLK[i] <= ~multiCLK[i]; end
end
end
endgenerate
//如果频率差到 80ppm参数是 8000640/1000080/8000640 [pass]
//如果频率差到120ppm参数是 8000960/1000120/8000960 [pass]
//如果频率差到160ppm参数是 8001280/1000160/8001280 [pass]
//如果频率差到168ppm参数是 8001344/1000168/8001344 [pass]
//如果频率差到176ppm参数是 8001408/1000176/8001408 [pass]
//如果频率差到-176ppm参数是 7998592/ 999824/7998592 [pass]
//如果频率差到180ppm参数是 8001440/1000180/8001440 [pass]
//如果频率差到-180ppm参数是 7998560/ 999820/7998560 [pass]
//如果频率差到181ppm参数是 8001448/1000181/8001448 [failed] //tc29, tc30联合测试,tc30最后几个字节不过, 单测能过
//如果频率差到-181ppm参数是 7998552/ 999819/7998552 [failed] //同上
//如果频率差到182ppm参数是 8001456/1000182/8001456 [failed]
//如果频率差到-182ppm参数是 7998544/ 999818/7998544 [failed] //单测, tc30下行是对的,上行发生错误
//如果频率差到184ppm参数是 8001472/1000184/8001472 [failed] //差得字节数不多大概在180ppm上下
//如果频率差到-184ppm参数是 7998528/ 999816/7998528 [failed]
initial begin
forever begin #7998560 clock2 <= ~clock2; end
end
generate
for( genvar i = 0; i < 16; i = i + 1 ) begin
initial begin
multiCLK2[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin
#999820
;
end
forever begin #7998560 multiCLK2[i] <= ~multiCLK2[i]; end
end end
end end
endgenerate endgenerate
@@ -473,7 +438,7 @@ initial
begin begin
spidata_file = $fopen("spi_trans_data.txt", "w"); spidata_file = $fopen("spi_trans_data.txt", "w");
if (!spidata_file) $display("文件打开失败"); if (!spidata_file) $display("文件打开失败");
$dumpfile("./tb/build/wave.fst"); //生成的vcd文件名称 $dumpfile("./generated/wave.vcd"); //生成的vcd文件名称
$dumpvars(0, ShinTopSpiTb);//tb模块名称 $dumpvars(0, ShinTopSpiTb);//tb模块名称
end end
@@ -485,7 +450,7 @@ always @(negedge reset) begin
_reset_deactive <= 1'b1; _reset_deactive <= 1'b1;
end end
`define SCKFRE #64000000 `define SCKFRE #640
reg sck = 0; reg sck = 0;
@@ -560,13 +525,13 @@ end
always @(posedge clock) begin always @(posedge clock) begin
if( isReq & sck == 0 ) begin if( isReq & sck == 0 ) begin
isBusy <= #500000 1'b1; isBusy <= #5 1'b1;
transCnt <= #500000 0; transCnt <= #5 0;
byteCnt <= #500000 ~12'b0; byteCnt <= #5 ~12'b0;
bitCnt <= #500000 ~3'b0; bitCnt <= #5 ~3'b0;
spi_csn[idx] <= #500000 1'b0; spi_csn[idx] <= #5 1'b0;
exChangeRego <= txBuf[0]; exChangeRego <= txBuf[0];
end end
end end
@@ -613,8 +578,8 @@ always @(posedge sck) begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso}; exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end end
end else begin end else begin
isBusy <= #500000 1'b0; isBusy <= #5 1'b0;
spi_csn[idx] <= #500000 1'b1; spi_csn[idx] <= #5 1'b1;
end end
end end
end end
@@ -633,13 +598,13 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
length <= slength + 3; length <= slength + 3;
idx <= sidx; idx <= sidx;
#500000 #5
@(negedge sck) @(negedge sck)
isReq <= 1; isReq <= 1;
@(posedge sck) #500000 @(posedge sck) #5
isReq <= 0; isReq <= 0;
@( negedge isBusy) #100000000 @( negedge isBusy) #1000
begin begin
//$fwrite(spidata_file, "------------%5t------------\n", $realtime); //$fwrite(spidata_file, "------------%5t------------\n", $realtime);
$fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n", $fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n",
@@ -918,13 +883,13 @@ task wait_comm_finished(input [16:0] dev_idx);
length = 8'h07; length = 8'h07;
idx = `IF_IQSPI(dev_idx); idx = `IF_IQSPI(dev_idx);
#500000 #5
@(negedge sck) @(negedge sck)
isReq <= 1; isReq <= 1;
@(posedge sck) #500000 @(posedge sck) #5
isReq <= 0; isReq <= 0;
@( negedge isBusy) #100000000 @( negedge isBusy) #1000
begin begin
end end
@@ -938,17 +903,17 @@ task wait_comm_finished(input [16:0] dev_idx);
length = 8'h07; length = 8'h07;
idx = `IF_IQSPI(dev_idx); idx = `IF_IQSPI(dev_idx);
#500000 #5
@(negedge sck) @(negedge sck)
isReq <= 1; isReq <= 1;
@(posedge sck) #500000 @(posedge sck) #5
isReq <= 0; isReq <= 0;
@( negedge isBusy) #100000000 @( negedge isBusy) #1000
begin begin
end end
#100000000 #2000
//$display("%x %x", rxBuf[3], rxBuf[6]); //$display("%x %x", rxBuf[3], rxBuf[6]);
if ((rxBuf[3] & 8'h02) == 8'h02) if ((rxBuf[3] & 8'h02) == 8'h02)
begin begin
@@ -959,7 +924,7 @@ task wait_comm_finished(input [16:0] dev_idx);
$display("error occur"); $display("error occur");
is_run = 0; is_run = 0;
end end
if (($realtime - st) >= 500000000000.0) if (($realtime - st) >= 5000000.0)
begin begin
$display("comm timeout."); $display("comm timeout.");
is_run = 0; is_run = 0;
@@ -971,7 +936,7 @@ endtask
initial begin initial begin
#50000000 #1000
`ifdef ENABLE_REG_RW1_TEST `ifdef ENABLE_REG_RW1_TEST
/*--------------------------------------------------------------------------------------------------------- /*---------------------------------------------------------------------------------------------------------
@@ -1124,7 +1089,7 @@ initial begin
`include "tc_runlist.vh" `include "tc_runlist.vh"
#100000000000 #1000000
$display("Testcase Finished! Time Out !!!"); $display("Testcase Finished! Time Out !!!");
$fclose(spidata_file); $fclose(spidata_file);
$stop; $stop;

File diff suppressed because it is too large Load Diff

View File

@@ -47,9 +47,9 @@ if __name__ == '__main__':
#add_tc_2_runlist(errorPkt.tc38()) #add_tc_2_runlist(errorPkt.tc38())
#add_tc_2_runlist(base.tc1()) add_tc_2_runlist(base.tc1())
#add_tc_2_runlist(base.tc2()) add_tc_2_runlist(base.tc2())
#add_tc_2_runlist(base.tc3()) add_tc_2_runlist(base.tc3())
#add_tc_2_runlist(base.tc4()) #add_tc_2_runlist(base.tc4())
#add_tc_2_runlist(base.tc5()) #add_tc_2_runlist(base.tc5())
#add_tc_2_runlist(base.tc6()) #add_tc_2_runlist(base.tc6())
@@ -76,8 +76,8 @@ if __name__ == '__main__':
#add_tc_2_runlist(base.tc27()) #add_tc_2_runlist(base.tc27())
#add_tc_2_runlist(base.tc28()) #add_tc_2_runlist(base.tc28())
#add_tc_2_runlist(base.tc29()) #add_tc_2_runlist(base.tc29())
add_tc_2_runlist(base.tc29()) #add_tc_2_runlist(base.tc29())
add_tc_2_runlist(base.tc30()) #add_tc_2_runlist(base.tc30())
#add_tc_2_runlist(broadcast.tc1()) #add_tc_2_runlist(broadcast.tc1())
@@ -111,7 +111,7 @@ if __name__ == '__main__':
#add_tc_2_runlist(ebmmu.tc16()) #add_tc_2_runlist(ebmmu.tc16())
#add_tc_2_runlist(ebmmu.tc17()) #add_tc_2_runlist(ebmmu.tc17())
#add_tc_2_runlist(ebmmu.tc18()) #add_tc_2_runlist(ebmmu.tc18())
add_tc_2_runlist(ebmmu.tc19()) #add_tc_2_runlist(ebmmu.tc19())
#add_tc_2_runlist(watchdog.tc1()) #add_tc_2_runlist(watchdog.tc1())
#add_tc_2_runlist(watchdog.tc2()) #add_tc_2_runlist(watchdog.tc2())

View File

@@ -305,6 +305,26 @@ def gen_slv_dev_num(num):
gen_file_def = "slave_dev_def" gen_file_def = "slave_dev_def"
code = ""
for id in range(num - 1):
code = code + __GenDevice(id)
code = code + __GenDevice(num - 1, True)
genPkt.addAfterExc(code)
genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
def gen_slv_dev_for_clk(num):
__gen_slv_dev_predef(num)
genPkt = GenPkt()
genPkt.clean()
gen_file_def = "slave_dev_def"
code = "" code = ""
for id in range(num - 1): for id in range(num - 1):
if id == 1: if id == 1:
@@ -320,8 +340,6 @@ def gen_slv_dev_num(num):
def teardown(): def teardown():
#add_tc_2_runlist("") #add_tc_2_runlist("")
pass pass