未完成清理tx，txready初始化为true
This commit is contained in:
RuigeLee
@@ -8,19 +8,25 @@ class Transmit_Enq_Ctrl_Bundle extends Bundle{
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}
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class Transmit_Deq_Ctrl_Bundle extends Bundle{
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class Transmit_Deq_Req_Bundle extends Bundle{
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}
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class Transmit_Deq_Resp_Bundle extends Bundle{
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}
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class Transmit_Enq_Bundle extends Bundle{
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val data = Decoupled(UInt(32.W))
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val ctrl = Decoupled(new RevBuff_Enq_Ctrl_Bundle)
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val ctrl = Decoupled(new Transmit_Enq_Ctrl_Bundle)
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}
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class Transmit_Deq_Bundle extends Bundle{
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val data = Decoupled(UInt(32.W))
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val ctrl = Decoupled(new RevBuff_Deq_Ctrl_Bundle)
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val req = Decoupled(new Transmit_Deq_Req_Bundle)
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val resp = Flipped(Decoupled(new Transmit_Deq_Resp_Bundle))
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}
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@@ -711,8 +711,8 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
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wishbone.io.r_TxEn := r_TxEn
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wishbone.io.r_RxEn := r_RxEn
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TxB_IRQ := wishbone.io.TxB_IRQ
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TxE_IRQ := wishbone.io.TxE_IRQ
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TxB_IRQ := false.B
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TxE_IRQ := false.B
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RxB_IRQ := false.B
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RxE_IRQ := false.B
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@@ -45,10 +45,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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//Register
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val r_TxEn = Input(Bool()) // Transmit enable
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// Interrupts
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val TxB_IRQ = Output(Bool())
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val TxE_IRQ = Output(Bool())
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val BlockingTxStatusWrite = Output(Bool())
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val TxUsedData = Input(Bool()) // Transmit packet used data
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@@ -150,10 +146,10 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val TxStartFrm_wb = RegInit(false.B); io.TxStartFrm_wb := TxStartFrm_wb
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val TxStatus = RegInit(0.U(4.W)) //[14:11]
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when( io.txEnq.ctrl.fire ){
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when( io.txEnq.req.fire ){
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TxStartFrm_wb := true.B
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} .elsewhen(io.TxStartFrm_syncb){
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TxStartFrm_wb := false.B
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@@ -166,10 +162,13 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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TxEndFrm_wb := false.B
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}
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when( io.txEnq.ctrl.fire ){
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TxStatus := Cat(txBuffDesc.irq, txBuffDesc.wr, txBuffDesc.pad, txBuffDesc.crc) // Latching status from the tx buffer descriptor Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
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TxLength := io.txEnq.ctrl.bits.txLength //Latching length from the buffer descriptor;
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LatchedTxLength := io.txEnq.ctrl.bits.txLength
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when( io.txEnq.req.fire ){
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TxStatus :=
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Cat(
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io.txEnq.req.bits.irq, io.txEnq.req.bits.wr, io.txEnq.req.bits.pad, io.txEnq.req.bits.crc
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)
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TxLength := io.txEnq.req.bits.txLength
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LatchedTxLength := io.txEnq.req.bits.txLength
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} .elsewhen( io.txEnq.data.fire ){
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when( TxLength < 4.U ){
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TxLength := 0.U
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@@ -178,8 +177,66 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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}
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}
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tx_fifo.io.data_in := io.tlMst.D.bits.data
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tx_fifo.io.write := io.tlMst.D.fire & io.tlMst.D.bits.opcode === 1.U
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val txRespValid := RegInit(false.B)
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io.txEnq.resp.valid := txRespValid
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io.txEnq.resp.bits :=
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RegEnable(
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Cat(LatchedTxLength, 0.U(1.W), TxStatus, 0.U(2.W), false.B, io.RetryCntLatched, io.RetryLimit, io.LateCollLatched, io.DeferLatched, io.CarrierSenseLost),
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TxRetryPulse | TxDonePulse | TxAbortPulse
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)
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when( io.txEnq.resp.fire ){
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txRespValid := false.B
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} .elsewhen( TxRetryPulse | TxDonePulse | TxAbortPulse ){
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txRespValid := true.B
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}
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// // Latching READY status of the Tx buffer descriptor
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// when(TxBDRead){ // TxBDReady is sampled only once at the beginning.
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// TxBDReady := txBuffDesc.rd & (txBuffDesc.len > 4.U)
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// } .elsewhen(ResetTxBDReady){ // Only packets larger then 4 bytes are transmitted.
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// TxBDReady := false.B
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// }
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val txEnqReqReady = RegInit(true.B); io.txEnq.req.ready := txEnqReqReady
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val StartTxBDRead = (TxRetryPacket_NotCleared | TxDonePacket | TxAbortPacket) & ~TxBDReady // Reading the Tx buffer descriptor
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when(io.txEnq.req.fire){
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txEnqReqReady := false.B
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} .elsewhen(StartTxBDRead){
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txEnqReqReady := true.B
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}
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// Writing status back to the Tx buffer descriptor
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TxStatusWrite := (TxDonePacket | TxAbortPacket)
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// Status writing must occur only once. Meanwhile it is blocked.
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when(~io.TxDoneSync & ~io.TxAbortSync){
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BlockingTxStatusWrite := false.B
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} .elsewhen(TxStatusWrite){
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BlockingTxStatusWrite := true.B
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}
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io.txEnq.data.ready := ReadTxDataFromFifoSyncPluse & ~tx_fifo.io.empty
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@@ -198,28 +255,18 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val TxRetryPacket = RegInit(false.B)
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val TxRetryPacket_NotCleared = RegInit(false.B)
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val TxDonePacket = RegInit(false.B)
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val TxDonePacket_NotCleared = RegInit(false.B)
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val TxAbortPacket = RegInit(false.B)
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val TxAbortPacket_NotCleared = RegInit(false.B)
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val TxBDReady = RegInit(false.B)
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val TxBDAddress = RegInit(0.U(7.W)) //[7:1]
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val ReadTxDataFromFifoSyncPluse = io.ReadTxDataFromFifo_sync & ~RegNext(io.ReadTxDataFromFifo_sync, false.B)
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val (_, _, isLastD, transDCnt) = edgeOut.count(io.tlMst.D)
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val tx_fifo = Module( new MacFifo(dw = 32, dp = 16) )
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val TxB_IRQ = RegInit(false.B); io.TxB_IRQ := TxB_IRQ
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val TxE_IRQ = RegInit(false.B); io.TxE_IRQ := TxE_IRQ
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val TxBDRead = RegInit(true.B)
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val TxStatusWrite = Wire(Bool())
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val TxLength = RegInit(0.U(16.W))
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val TxStatus = RegInit(0.U(4.W)) //[14:11]
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val TxRetryPulse = io.TxRetrySync & ~RegNext(io.TxRetrySync, false.B)
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val TxDonePulse = io.TxDoneSync & ~RegNext(io.TxDoneSync, false.B)
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@@ -228,161 +275,52 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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val BlockingTxStatusWrite = RegInit(false.B); io.BlockingTxStatusWrite := BlockingTxStatusWrite
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val BlockingTxBDRead = RegInit(false.B)
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val BDWrite = RegInit(0.U(4.W)) // BD Write Enable for access from WISHBONE side
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val BDRead = RegInit(false.B) // BD Read access from WISHBONE side
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val TxEndFrm_wb = RegInit(false.B); io.TxEndFrm_wb := TxEndFrm_wb
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// Delayed stage signals
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val r_TxEn_q = RegNext(io.r_TxEn, false.B)
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def StateIdle = 0.U(3.W)
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def StateWB = 1.U(3.W)
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def StateTX = 2.U(3.W)
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val stateNxt = RegInit( StateWB )
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val stateCur = RegNext( stateNxt, StateIdle )
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val TxAbortPacketBlocked = RegInit(false.B)
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val ram_addr = RegInit(0.U(8.W))
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val ram_di = RegInit(0.U(32.W))
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val TxPointerRead = RegInit(false.B)
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val TxEn_needed = RegInit(false.B)
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val BlockReadTxDataFromMemory = RegInit(false.B)
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val ReadTxDataFromMemory = RegInit(false.B)
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val MasterWbTX = RegInit(false.B)
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val TxPointerMSB = RegInit(0.U(30.W)) //[31:2]
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// Generic synchronous single-port RAM interface
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val bd_ram = Module(new MacSRAM)
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val txBuffDesc = bd_ram.io.dato.asTypeOf(new TxBuffDesc)
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bd_ram.io.we :=
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Mux1H(Seq(
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(stateNxt === StateWB & stateCur === StateWB) -> BDWrite,
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(TxStatusWrite ) -> "b1111".U
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)).asBools
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bd_ram.io.oe :=
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Mux1H(Seq(
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(( stateNxt === StateWB ) & ( stateCur === StateWB )) -> BDRead,
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(( stateNxt === StateTX ) & ( stateCur === StateTX )) -> (TxBDRead | TxPointerRead),
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))
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bd_ram.io.addr := ram_addr
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bd_ram.io.di := ram_di
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when(~TxBDReady & io.r_TxEn & stateNxt === StateWB & stateCur =/= StateWB){
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TxEn_needed := true.B
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} .elsewhen(TxPointerRead & stateNxt === StateTX & stateCur === StateTX){
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TxEn_needed := false.B
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}
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// Enabling access to the RAM for three devices.
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// Switching between three stages depends on enable signals
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switch( stateCur ){
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is(StateIdle){
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when( TxEn_needed === false.B ){
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stateNxt := StateWB // Idle state. We go to WbEn access stage.
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ram_addr := io.tlSlv.A.bits.address(9,2) // [11:2 ] -> [9:2]
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ram_di := io.tlSlv.A.bits.data
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BDWrite := io.tlSlv.A.bits.mask & Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.address(10) & ((io.tlSlv.A.bits.opcode === 0.U) || (io.tlSlv.A.bits.opcode === 1.U)) )
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BDRead := io.tlSlv.A.bits.mask.orR & io.tlSlv.A.valid & io.tlSlv.A.bits.address(10) & (io.tlSlv.A.bits.opcode === 4.U) // 0x400 - 0x7FF
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}
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}
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is(StateWB){
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when( TxEn_needed ){
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stateNxt := StateTX // wb access stage, r_RxEn is disabled but r_TxEn is enabled
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ram_addr := Cat(TxBDAddress, TxPointerRead) //[7,1] + [0]
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ram_di := Cat(LatchedTxLength, 0.U(1.W), TxStatus, 0.U(2.W), false.B, io.RetryCntLatched, io.RetryLimit, io.LateCollLatched, io.DeferLatched, io.CarrierSenseLost)
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when( io.TxAbortSync & (~TxAbortPacketBlocked) ){
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TxAbortPacket := true.B
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} .otherwise{
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stateNxt := StateIdle // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
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}
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}
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is(StateTX){
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when( true.B ){
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stateNxt := StateWB // TxEn access stage (we always go to wb access stage)
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ram_addr := io.tlSlv.A.bits.address(9,2) //[11:2 ] ->[9:2]
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ram_di := io.tlSlv.A.bits.data
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BDWrite := io.tlSlv.A.bits.mask & Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.address(10) & ((io.tlSlv.A.bits.opcode === 0.U) || (io.tlSlv.A.bits.opcode === 1.U)) )
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BDRead := io.tlSlv.A.bits.mask.orR & io.tlSlv.A.valid & io.tlSlv.A.bits.address(10) & (io.tlSlv.A.bits.opcode === 4.U)
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}
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}
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TxAbortPacket := false.B
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}
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val ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse
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// Latching READY status of the Tx buffer descriptor
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when(stateNxt === StateTX & stateCur === StateTX & TxBDRead){ // TxBDReady is sampled only once at the beginning.
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TxBDReady := txBuffDesc.rd & (txBuffDesc.len > 4.U)
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} .elsewhen(ResetTxBDReady){ // Only packets larger then 4 bytes are transmitted.
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TxBDReady := false.B
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when(~io.TxAbortSync & RegNext(io.TxAbortSync, false.B)){
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TxAbortPacketBlocked := false.B
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} .elsewhen(TxAbortPacket){
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TxAbortPacketBlocked := true.B
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}
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val StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady // Reading the Tx buffer descriptor
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val TxRetryPacketBlocked = RegInit(false.B)
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when( io.TxRetrySync & ~TxRetryPacketBlocked ){
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TxRetryPacket := true.B
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} .otherwise{
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TxRetryPacket := false.B
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}
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when(StartTxBDRead){
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TxBDRead := true.B
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} .elsewhen(TxBDReady){
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TxBDRead := false.B
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}
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// Reading Tx BD Pointer
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when(TxBDRead & TxBDReady){
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TxPointerRead := true.B
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} .elsewhen(stateCur === StateTX){
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TxPointerRead := false.B
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TxRetryPacket_NotCleared := false.B
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} .elsewhen( io.TxRetrySync & ~TxRetryPacketBlocked ){
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TxRetryPacket_NotCleared := true.B
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}
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// Writing status back to the Tx buffer descriptor
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TxStatusWrite := (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & stateNxt === StateTX & stateCur === StateTX & ~BlockingTxStatusWrite
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// Status writing must occur only once. Meanwhile it is blocked.
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when(~io.TxDoneSync & ~io.TxAbortSync){
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BlockingTxStatusWrite := false.B
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} .elsewhen(TxStatusWrite){
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BlockingTxStatusWrite := true.B
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when( ~io.TxRetrySync & RegNext(io.TxRetrySync, false.B) ){
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TxRetryPacketBlocked := false.B
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} .elsewhen(TxRetryPacket){
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TxRetryPacketBlocked := true.B
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}
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@@ -390,79 +328,22 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
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// TxBDRead state is activated only once.
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when(StartTxBDRead){
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BlockingTxBDRead := true.B
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} .elsewhen(~StartTxBDRead & ~TxBDReady){
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BlockingTxBDRead := false.B
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val TxDonePacketBlocked = RegInit(false.B)
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when( io.TxDoneSync & ~TxDonePacketBlocked ){
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TxDonePacket := true.B
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}.otherwise{
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TxDonePacket := false.B
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}
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when(stateNxt === StateTX & stateCur === StateTX & TxPointerRead){
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TxPointerMSB := bd_ram.io.dato(31,2) // Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched because TxPointerMSB is only used for word-aligned accesses.
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when( bd_ram.io.dato(1,0) =/= 0.U ){
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printf("Warning, force to align at tx ram")
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when(~io.TxDoneSync & RegNext(io.TxDoneSync, false.B)){
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TxDonePacketBlocked := false.B
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} .elsewhen(TxDonePacket){
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TxDonePacketBlocked := true.B
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}
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} .elsewhen( io.tlMst.D.fire & io.tlMst.D.bits.opcode === 1.U ){
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TxPointerMSB := TxPointerMSB + 1.U // TxPointer is word-aligned
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}
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val isTlMstBusy = RegInit(false.B)
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when( (TxLength === 0.U) | TxAbortPulse | TxRetryPulse){
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ReadTxDataFromMemory := false.B
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} .elsewhen(stateNxt === StateTX & stateCur === StateTX & TxPointerRead){
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ReadTxDataFromMemory := true.B
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}
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val ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
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when(
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(tx_fifo.io.almost_full | TxLength <= 4.U) & MasterWbTX & isTlMstBusy & (~(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared))){
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BlockReadTxDataFromMemory := true.B
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} .elsewhen(ReadTxDataFromFifoSyncPluse | TxDonePacket | TxAbortPacket | TxRetryPacket){
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BlockReadTxDataFromMemory := false.B
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}
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val TxError = io.RetryLimit | io.LateCollLatched | io.CarrierSenseLost
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// Tx Done Interrupt
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when(TxStatusWrite & TxIRQEn){
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TxB_IRQ := ~TxError
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} .otherwise{
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TxB_IRQ := false.B
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}
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// Tx Error Interrupt
|
||||
when(TxStatusWrite & TxIRQEn){
|
||||
TxE_IRQ := TxError
|
||||
} .otherwise{
|
||||
TxE_IRQ := false.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -557,196 +438,10 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
|
||||
|
||||
|
||||
|
||||
// Latching Tx buffer descriptor address
|
||||
when(io.r_TxEn & (~r_TxEn_q)){
|
||||
TxBDAddress := 0.U
|
||||
} .elsewhen(TxStatusWrite){
|
||||
when( TxStatusWrite & ~WrapTxStatusBit ){ //increase
|
||||
TxBDAddress := TxBDAddress + 1.U
|
||||
} .otherwise{ //wrap
|
||||
TxBDAddress := 0.U
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val TxAbortPacketBlocked = RegInit(false.B)
|
||||
|
||||
when(
|
||||
io.TxAbortSync & (~TxAbortPacketBlocked) & MasterWbTX & io.tlMst.D.fire & isLastD |
|
||||
io.TxAbortSync & (~TxAbortPacketBlocked) & (~MasterWbTX) ){
|
||||
TxAbortPacket := true.B
|
||||
} .otherwise{
|
||||
TxAbortPacket := false.B
|
||||
}
|
||||
|
||||
|
||||
when(stateNxt === StateTX & stateCur === StateTX & TxAbortPacket_NotCleared){
|
||||
TxAbortPacket_NotCleared := false.B
|
||||
} .elsewhen(
|
||||
io.TxAbortSync & (~TxAbortPacketBlocked) & MasterWbTX & io.tlMst.D.fire & isLastD |
|
||||
io.TxAbortSync & (~TxAbortPacketBlocked) & (~MasterWbTX) ){
|
||||
TxAbortPacket_NotCleared := true.B
|
||||
}
|
||||
|
||||
when(~io.TxAbortSync & RegNext(io.TxAbortSync, false.B)){
|
||||
TxAbortPacketBlocked := false.B
|
||||
} .elsewhen(TxAbortPacket){
|
||||
TxAbortPacketBlocked := true.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
val TxRetryPacketBlocked = RegInit(false.B)
|
||||
|
||||
when(
|
||||
io.TxRetrySync & ~TxRetryPacketBlocked & MasterWbTX & io.tlMst.D.fire & isLastD |
|
||||
io.TxRetrySync & ~TxRetryPacketBlocked & ~MasterWbTX ){
|
||||
TxRetryPacket := true.B
|
||||
} .otherwise{
|
||||
TxRetryPacket := false.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
when(StartTxBDRead){
|
||||
TxRetryPacket_NotCleared := false.B
|
||||
} .elsewhen(
|
||||
io.TxRetrySync & ~TxRetryPacketBlocked & MasterWbTX & io.tlMst.D.fire & isLastD |
|
||||
io.TxRetrySync & ~TxRetryPacketBlocked & ~MasterWbTX ){
|
||||
TxRetryPacket_NotCleared := true.B
|
||||
}
|
||||
|
||||
|
||||
when( ~io.TxRetrySync & RegNext(io.TxRetrySync, false.B) ){
|
||||
TxRetryPacketBlocked := false.B
|
||||
} .elsewhen(TxRetryPacket){
|
||||
TxRetryPacketBlocked := true.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
val TxDonePacketBlocked = RegInit(false.B)
|
||||
|
||||
when(
|
||||
io.TxDoneSync & ~TxDonePacketBlocked & MasterWbTX & io.tlMst.D.fire & isLastD |
|
||||
io.TxDoneSync & ~TxDonePacketBlocked & ~MasterWbTX ){
|
||||
TxDonePacket := true.B
|
||||
}.otherwise{
|
||||
TxDonePacket := false.B
|
||||
}
|
||||
|
||||
when(stateNxt === StateTX & stateCur === StateTX & TxDonePacket_NotCleared){
|
||||
TxDonePacket_NotCleared := false.B
|
||||
} .elsewhen(
|
||||
io.TxDoneSync & ~TxDonePacketBlocked & MasterWbTX & io.tlMst.D.fire & isLastD |
|
||||
io.TxDoneSync & ~TxDonePacketBlocked & ~MasterWbTX ){
|
||||
TxDonePacket_NotCleared := true.B
|
||||
}
|
||||
|
||||
|
||||
when(~io.TxDoneSync & RegNext(io.TxDoneSync, false.B)){
|
||||
TxDonePacketBlocked := false.B
|
||||
} .elsewhen(TxDonePacket){
|
||||
TxDonePacketBlocked := true.B
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val slvAInfo = RegEnable( io.tlSlv.A.bits, io.tlSlv.A.fire )
|
||||
val slvDValid = RegInit(false.B); io.tlSlv.D.valid := slvDValid
|
||||
val slvDDat = Reg(UInt(32.W))
|
||||
|
||||
|
||||
|
||||
when( io.tlSlv.D.fire ){
|
||||
slvDValid := false.B
|
||||
} .elsewhen(io.tlSlv.A.fire){
|
||||
slvDValid := true.B
|
||||
slvDDat := bd_ram.io.dato
|
||||
}
|
||||
|
||||
when(slvAInfo.opcode === 4.U) {
|
||||
io.tlSlv.D.bits := edgeIn.AccessAck(slvAInfo, slvDDat)
|
||||
} .otherwise {
|
||||
io.tlSlv.D.bits := edgeIn.AccessAck(slvAInfo)
|
||||
}
|
||||
|
||||
io.tlSlv.A.ready := RegNext(stateNxt === StateWB & Mux( stateCur === StateWB , BDWrite.orR, BDRead ))
|
||||
|
||||
assert( ~(io.tlSlv.A.ready & ~io.tlSlv.A.valid) )
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val mstAValid = RegInit(false.B)
|
||||
val mstABits = Reg(new TLBundleA(edgeOut.bundle))
|
||||
|
||||
|
||||
when( io.tlMst.A.fire ){
|
||||
mstAValid := false.B
|
||||
}
|
||||
.elsewhen( MasterWbTX & ~isTlMstBusy ){
|
||||
mstAValid := true.B
|
||||
mstABits :=
|
||||
edgeOut.Get(
|
||||
fromSource = 0.U,
|
||||
toAddress = TxPointerMSB << 2,
|
||||
lgSize = log2Ceil(32/8).U,
|
||||
)._2
|
||||
}
|
||||
|
||||
when( io.tlMst.A.fire ){
|
||||
isTlMstBusy := true.B
|
||||
} .elsewhen( io.tlMst.D.fire ){
|
||||
isTlMstBusy := false.B
|
||||
}
|
||||
|
||||
when( ~MasterWbTX ){
|
||||
when(ReadTxDataFromMemory_2) {
|
||||
MasterWbTX := true.B
|
||||
}
|
||||
} .elsewhen( MasterWbTX ){ //1 A + 1.4D memory to fifo
|
||||
when( io.tlMst.D.fire & isLastD & ~ReadTxDataFromMemory_2 ){
|
||||
MasterWbTX := false.B
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
when(io.tlMst.D.fire & io.tlMst.D.bits.opcode === 1.U) { assert( MasterWbTX ) }
|
||||
|
||||
val tlMstAValid_dbg = RegInit(true.B)
|
||||
io.tlMst.A.valid := mstAValid & tlMstAValid_dbg
|
||||
io.tlMst.A.bits := mstABits
|
||||
|
||||
|
||||
val tlMstDReady = RegInit(true.B)
|
||||
|
||||
io.tlMst.D.ready := tlMstDReady
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user