From 0b84a1dc6f6512028a0062d18ea1bb217ce7a14c Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Thu, 7 Aug 2025 10:27:37 +0800 Subject: [PATCH] =?UTF-8?q?=E4=B8=8A=E7=94=B5=E5=A4=8D=E4=BD=8D=E7=8A=B6?= =?UTF-8?q?=E6=80=81=E4=B8=8B=EF=BC=8C=E4=B8=8A=E4=B8=8B=E8=A1=8C=E7=9B=B4?= =?UTF-8?q?=E9=80=9A=EF=BC=8C=E8=AE=BE=E7=BD=AE=E4=B8=BA=E4=B8=BB=E7=AB=99?= =?UTF-8?q?=E6=88=96=E8=80=85=E5=86=99=E6=B8=85=E5=A4=8D=E4=BD=8D=E4=B8=AD?= =?UTF-8?q?=E6=96=AD=E5=8F=AF=E4=BB=A5=E8=A7=A3=E9=99=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 2 ++ src/main/scala/backBoard/shin/ShinTop.scala | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 13b195b..c1e812a 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -194,6 +194,7 @@ class InterfaceIO extends Bundle{ val isSMReset = Output( Vec(8, Bool()) ) val latchPin = Input(Vec(2, Bool())) + val isPoReset = Output(Bool()) } @@ -1058,6 +1059,7 @@ trait InterfaceSystem{ this: InterfaceBase => if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) } } cReg.intStatus := Cat( intStatus.reverse ) + io.isPoReset := intStatus(31) cReg.intMode := Cat( diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index 505061d..86a5466 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -452,7 +452,7 @@ with ShinTopSlave with ShinTopWatchDog{ when( interface.io.cReg.modeSel === false.B ){ //slave - when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) ){ //硬件错误 + when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误 downCDRIn.io.serDat := false.B upCDRIn.io.serDat := false.B when( slaveParser.io.isLoop ){ //回环