diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 13b195b..c1e812a 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -194,6 +194,7 @@ class InterfaceIO extends Bundle{
   val isSMReset = Output( Vec(8, Bool()) )
 
   val latchPin = Input(Vec(2, Bool()))
+  val isPoReset = Output(Bool())
 }
 
 
@@ -1058,6 +1059,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
     if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) }
   }
   cReg.intStatus := Cat( intStatus.reverse )
+  io.isPoReset := intStatus(31)
 
   cReg.intMode :=
     Cat(
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 505061d..86a5466 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -452,7 +452,7 @@ with ShinTopSlave
 with ShinTopWatchDog{
 
   when( interface.io.cReg.modeSel === false.B ){ //slave
-    when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) ){ //硬件错误
+    when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
       downCDRIn.io.serDat  := false.B
       upCDRIn.io.serDat  := false.B
       when( slaveParser.io.isLoop ){ //回环