diff --git a/src/main/scala/backBoard/ebus/b8b10.scala b/src/main/scala/backBoard/ebus/b8b10.scala
new file mode 100644
index 0000000..af8927a
--- /dev/null
+++ b/src/main/scala/backBoard/ebus/b8b10.scala
@@ -0,0 +1,56 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class b8b10Encode extends Module with RequireAsyncReset{
+  val io = IO(new Bundle{
+    val dataIn = Input(UInt(8.W))
+    val isEnable = Input(Bool())
+    val dataOut = Output(UInt(10.W))
+  })
+
+  val rd = RegInit(false.B)
+  
+  val rdCalNext = Wire(SInt(8.W))
+  val rdCal = RegNext(rdCalNext, 0.S(8.W))
+
+  val b5b6LookUp = Mux1H(Seq(
+    (io.dataIn(4,0) === "b00000".U) -> Mux( rd, "b100111".U(6.W), "b011000".U(6.W) ),
+    (io.dataIn(4,0) === "b00001".U) -> Mux( rd, "b011101".U(6.W), "b100010".U(6.W) ),
+    (io.dataIn(4,0) === "b00010".U) -> Mux( rd, "b101101".U(6.W), "b010010".U(6.W) ),
+    (io.dataIn(4,0) === "b00011".U) -> "b110001".U(6.W),
+    (io.dataIn(4,0) === "b00100".U) -> Mux( rd, "b110101".U(6.W), "b001010".U(6.W) ),
+    (io.dataIn(4,0) === "b00101".U) -> "b101001".U(6.W),
+    (io.dataIn(4,0) === "b00110".U) -> "b011001".U(6.W),
+    (io.dataIn(4,0) === "b00111".U) -> Mux( rd, "b111000".U(6.W), "b000111".U(6.W) ),
+    (io.dataIn(4,0) === "b01000".U) -> Mux( rd, "b111001".U(6.W), "b000110".U(6.W) ),
+    (io.dataIn(4,0) === "b01001".U) -> "b100101".U(6.W),
+    (io.dataIn(4,0) === "b01010".U) -> "b010101".U(6.W),
+    (io.dataIn(4,0) === "b01011".U) -> "b110100".U(6.W),
+    (io.dataIn(4,0) === "b01100".U) -> "b001101".U(6.W),
+    (io.dataIn(4,0) === "b01101".U) -> "b101100".U(6.W),
+    (io.dataIn(4,0) === "b01110".U) -> "b011100".U(6.W),
+    (io.dataIn(4,0) === "b01111".U) -> Mux( rd, "b010111".U(6.W), "b101000".U(6.W) ),
+    (io.dataIn(4,0) === "b10000".U) -> Mux( rd, "b011011".U(6.W), "b100100".U(6.W) ),
+    (io.dataIn(4,0) === "b10001".U) -> "b100011".U(6.W),
+    (io.dataIn(4,0) === "b10010".U) -> "b010011".U(6.W),
+    (io.dataIn(4,0) === "b10011".U) -> "b110010".U(6.W),
+    (io.dataIn(4,0) === "b10100".U) -> "b001011".U(6.W),
+    (io.dataIn(4,0) === "b10101".U) -> "b101010".U(6.W),
+    (io.dataIn(4,0) === "b10110".U) -> "b011010".U(6.W),
+    (io.dataIn(4,0) === "b10111".U) -> Mux( rd, "b111010".U(6.W), "b000101".U(6.W) ),
+    (io.dataIn(4,0) === "b11000".U) -> Mux( rd, "b110011".U(6.W), "b001100".U(6.W) ),
+    (io.dataIn(4,0) === "b11001".U) -> "b100110".U(6.W),
+    (io.dataIn(4,0) === "b11010".U) -> "b010110".U(6.W),
+    (io.dataIn(4,0) === "b11011".U) -> Mux( rd, "b110110".U(6.W), "b001001".U(6.W) ),
+    (io.dataIn(4,0) === "b11100".U) -> "b001110".U(6.W),
+    (io.dataIn(4,0) === "b11101".U) -> Mux( rd, "b101110".U(6.W), "b010001".U(6.W) ),
+    (io.dataIn(4,0) === "b11110".U) -> Mux( rd, "b011110".U(6.W), "b100001".U(6.W) ),
+    (io.dataIn(4,0) === "b11111".U) -> Mux( rd, "b101011".U(6.W), "b010100".U(6.W) )
+  ))
+
+
+}
+