compile pass
This commit is contained in:
RuigeLee
@@ -14,7 +14,7 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
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val tlMasterNode =
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TLManagerNode(Seq(TLSlavePortParameters.v1(
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managers = Seq(TLSlaveParameters.v1(
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address = Seq(AddressSet(0x30000000L, 0x0FFFL)),
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address = Seq(AddressSet(0x30000400L, 0x03FFL)),
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regionType = RegionType.VOLATILE,
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executable = false,
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fifoId = Some(2),
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@@ -34,10 +34,9 @@ class Mac(implicit p: Parameters) extends LazyModule with HasMacParameters{
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// DTS
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val dtsdevice = new SimpleDevice("mac",Seq("mac_0"))
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val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int))
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val ethReg = LazyModule(new MacReg)
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lazy val module = new MacImp(this)
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@@ -77,7 +76,7 @@ class MacImp(outer: Mac)(implicit p: Parameters) extends LazyModuleImp(outer) wi
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val ( slv_bus, slv_edge ) = outer.tlMasterNode.in.head
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val ( mst_bus, mst_edge ) = outer.tlClientNode.out.head
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val (int, _) = outer.int_node.out(0)
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@@ -179,7 +178,6 @@ val miim = Module(new MIIM)
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val RegDataOut = Wire(UInt(32.W))
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val r_RecSmall = Wire(Bool())
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val r_LoopBck = Wire(Bool())
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val r_TxEn = Wire(Bool())
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@@ -245,9 +243,7 @@ val LateCollLatched = Wire(Bool())
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val DeferLatched = Wire(Bool())
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val RstDeferLatched = Wire(Bool())
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val CarrierSenseLost = Wire(Bool())
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val RegCs = Wire(UInt(4.W))
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dontTouch(RegDataOut )
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dontTouch(r_RecSmall )
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dontTouch(r_LoopBck )
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dontTouch(r_TxEn )
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@@ -313,84 +309,78 @@ dontTouch(LateCollLatched )
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dontTouch(DeferLatched )
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dontTouch(RstDeferLatched )
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dontTouch(CarrierSenseLost )
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dontTouch(RegCs )
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val ethReg = Module(new MacReg)
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ethReg.io.DataIn := slv_bus.a.bits.data
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ethReg.io.Address := slv_bus.a.bits.address(9,2)
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ethReg.io.Rw := slv_bus.a.bits.opcode === 0.U | slv_bus.a.bits.opcode === 1.U
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// val ethReg = Module(new MacReg(outer.configNode))
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ethReg.io.Cs := RegCs
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ethReg.io.WCtrlDataStart := WCtrlDataStart
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ethReg.io.RStatStart := RStatStart
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ethReg.io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
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ethReg.io.Prsd := Prsd
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ethReg.io.NValid_stat := NValid_stat
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ethReg.io.Busy_stat := Busy_stat
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ethReg.io.LinkFail := LinkFail
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ethReg.io.TxB_IRQ := TxB_IRQ
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ethReg.io.TxE_IRQ := TxE_IRQ
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ethReg.io.RxB_IRQ := RxB_IRQ
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ethReg.io.RxE_IRQ := RxE_IRQ
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ethReg.io.Busy_IRQ := Busy_IRQ
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ethReg.io.RstTxPauseRq := RstTxPauseRq
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ethReg.io.TxCtrlEndFrm := TxCtrlEndFrm
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ethReg.io.StartTxDone := StartTxDone
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ethReg.io.TxClk := io.mtx_clk_pad_i
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ethReg.io.RxClk := io.mrx_clk_pad_i
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ethReg.io.SetPauseTimer := SetPauseTimer
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ethReg.io.dbg_dat := 0.U
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RegDataOut := ethReg.io.DataOut
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r_RecSmall := ethReg.io.r_RecSmall
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r_Pad := ethReg.io.r_Pad
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r_HugEn := ethReg.io.r_HugEn
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r_CrcEn := ethReg.io.r_CrcEn
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r_DlyCrcEn := ethReg.io.r_DlyCrcEn
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r_FullD := ethReg.io.r_FullD
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r_ExDfrEn := ethReg.io.r_ExDfrEn
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r_NoBckof := ethReg.io.r_NoBckof
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r_LoopBck := ethReg.io.r_LoopBck
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r_IFG := ethReg.io.r_IFG
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r_Pro := ethReg.io.r_Pro
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r_Bro := ethReg.io.r_Bro
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r_NoPre := ethReg.io.r_NoPre
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r_TxEn := ethReg.io.r_TxEn
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r_RxEn := ethReg.io.r_RxEn
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r_HASH0 := ethReg.io.r_HASH0
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r_HASH1 := ethReg.io.r_HASH1
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r_IPGT := ethReg.io.r_IPGT
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r_IPGR1 := ethReg.io.r_IPGR1
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r_IPGR2 := ethReg.io.r_IPGR2
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r_MinFL := ethReg.io.r_MinFL
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r_MaxFL := ethReg.io.r_MaxFL
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r_MaxRet := ethReg.io.r_MaxRet
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r_CollValid := ethReg.io.r_CollValid
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r_TxFlow := ethReg.io.r_TxFlow
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r_RxFlow := ethReg.io.r_RxFlow
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r_PassAll := ethReg.io.r_PassAll
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r_MiiNoPre := ethReg.io.r_MiiNoPre
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r_ClkDiv := ethReg.io.r_ClkDiv
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r_WCtrlData := ethReg.io.r_WCtrlData
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r_RStat := ethReg.io.r_RStat
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r_ScanStat := ethReg.io.r_ScanStat
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r_RGAD := ethReg.io.r_RGAD
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r_FIAD := ethReg.io.r_FIAD
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r_CtrlData := ethReg.io.r_CtrlData
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r_MAC := ethReg.io.r_MAC
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r_TxBDNum := ethReg.io.r_TxBDNum
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// io.int_o := ethReg.io.int_o
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int(0) := ethReg.io.int_o
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r_TxPauseTV := ethReg.io.r_TxPauseTV
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r_TxPauseRq := ethReg.io.r_TxPauseRq
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outer.ethReg.module.io.WCtrlDataStart := WCtrlDataStart
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outer.ethReg.module.io.RStatStart := RStatStart
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outer.ethReg.module.io.UpdateMIIRX_DATAReg := UpdateMIIRX_DATAReg
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outer.ethReg.module.io.Prsd := Prsd
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outer.ethReg.module.io.NValid_stat := NValid_stat
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outer.ethReg.module.io.Busy_stat := Busy_stat
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outer.ethReg.module.io.LinkFail := LinkFail
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outer.ethReg.module.io.TxB_IRQ := TxB_IRQ
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outer.ethReg.module.io.TxE_IRQ := TxE_IRQ
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outer.ethReg.module.io.RxB_IRQ := RxB_IRQ
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outer.ethReg.module.io.RxE_IRQ := RxE_IRQ
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outer.ethReg.module.io.Busy_IRQ := Busy_IRQ
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outer.ethReg.module.io.RstTxPauseRq := RstTxPauseRq
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outer.ethReg.module.io.TxCtrlEndFrm := TxCtrlEndFrm
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outer.ethReg.module.io.StartTxDone := StartTxDone
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outer.ethReg.module.io.TxClk := io.mtx_clk_pad_i
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outer.ethReg.module.io.RxClk := io.mrx_clk_pad_i
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outer.ethReg.module.io.SetPauseTimer := SetPauseTimer
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r_RecSmall := outer.ethReg.module.io.r_RecSmall
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r_Pad := outer.ethReg.module.io.r_Pad
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r_HugEn := outer.ethReg.module.io.r_HugEn
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r_CrcEn := outer.ethReg.module.io.r_CrcEn
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r_DlyCrcEn := outer.ethReg.module.io.r_DlyCrcEn
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r_FullD := outer.ethReg.module.io.r_FullD
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r_ExDfrEn := outer.ethReg.module.io.r_ExDfrEn
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r_NoBckof := outer.ethReg.module.io.r_NoBckof
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r_LoopBck := outer.ethReg.module.io.r_LoopBck
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r_IFG := outer.ethReg.module.io.r_IFG
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r_Pro := outer.ethReg.module.io.r_Pro
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r_Bro := outer.ethReg.module.io.r_Bro
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r_NoPre := outer.ethReg.module.io.r_NoPre
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r_TxEn := outer.ethReg.module.io.r_TxEn
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r_RxEn := outer.ethReg.module.io.r_RxEn
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r_HASH0 := outer.ethReg.module.io.r_HASH0
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r_HASH1 := outer.ethReg.module.io.r_HASH1
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r_IPGT := outer.ethReg.module.io.r_IPGT
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r_IPGR1 := outer.ethReg.module.io.r_IPGR1
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r_IPGR2 := outer.ethReg.module.io.r_IPGR2
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r_MinFL := outer.ethReg.module.io.r_MinFL
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r_MaxFL := outer.ethReg.module.io.r_MaxFL
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r_MaxRet := outer.ethReg.module.io.r_MaxRet
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r_CollValid := outer.ethReg.module.io.r_CollValid
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r_TxFlow := outer.ethReg.module.io.r_TxFlow
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r_RxFlow := outer.ethReg.module.io.r_RxFlow
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r_PassAll := outer.ethReg.module.io.r_PassAll
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r_MiiNoPre := outer.ethReg.module.io.r_MiiNoPre
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r_ClkDiv := outer.ethReg.module.io.r_ClkDiv
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r_WCtrlData := outer.ethReg.module.io.r_WCtrlData
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r_RStat := outer.ethReg.module.io.r_RStat
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r_ScanStat := outer.ethReg.module.io.r_ScanStat
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r_RGAD := outer.ethReg.module.io.r_RGAD
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r_FIAD := outer.ethReg.module.io.r_FIAD
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r_CtrlData := outer.ethReg.module.io.r_CtrlData
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r_MAC := outer.ethReg.module.io.r_MAC
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r_TxBDNum := outer.ethReg.module.io.r_TxBDNum
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// io.int_o := outer.ethReg.module.io.int_o
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// int(0) := outer.ethReg.module.io.int_o
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r_TxPauseTV := outer.ethReg.module.io.r_TxPauseTV
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r_TxPauseRq := outer.ethReg.module.io.r_TxPauseRq
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@@ -755,8 +745,6 @@ val rxethmac = Module(new MacRx)
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wishbone.io.r_TxEn := r_TxEn
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wishbone.io.r_RxEn := r_RxEn
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wishbone.io.r_TxBDNum := r_TxBDNum
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wishbone.io.RegDataOut := RegDataOut
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RegCs := wishbone.io.RegCs
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TxB_IRQ := wishbone.io.TxB_IRQ
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TxE_IRQ := wishbone.io.TxE_IRQ
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RxB_IRQ := wishbone.io.RxB_IRQ
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@@ -3,11 +3,14 @@ package MAC
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.regmapper._
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import freechips.rocketchip.tilelink._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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class MacRegIO extends Bundle{
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val DataIn = Input(UInt(32.W))
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val Address = Input(UInt(8.W))
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val Rw = Input(Bool())
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val Cs = Input(UInt(4.W))
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val WCtrlDataStart = Input(Bool())
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val RStatStart = Input(Bool())
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val UpdateMIIRX_DATAReg = Input(Bool())
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@@ -26,9 +29,7 @@ class MacRegIO extends Bundle{
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val TxClk = Input(Bool())
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val RxClk = Input(Bool())
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val SetPauseTimer = Input(Bool())
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val dbg_dat = Input(UInt(32.W)) // debug data input
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val DataOut = Output(UInt(32.W))
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val r_RecSmall = Output(Bool())
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val r_Pad = Output(Bool())
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val r_HugEn = Output(Bool())
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@@ -67,256 +68,330 @@ class MacRegIO extends Bundle{
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val r_CtrlData = Output(UInt(16.W))
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val r_MAC = Output(UInt(48.W))
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val r_TxBDNum = Output(UInt(8.W))
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val int_o = Output(Bool())
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// val int_o = Output(Bool())
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val r_TxPauseTV = Output(UInt(16.W))
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val r_TxPauseRq = Output(Bool())
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}
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class MacReg extends Module{
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class MacReg(implicit p: Parameters) extends LazyModule{
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// DTS
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val dtsdevice = new SimpleDevice("mac",Seq("mac_0"))
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val int_node = IntSourceNode(IntSourcePortSimple(num = 1, resources = dtsdevice.int))
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val configNode = TLRegisterNode(
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address = Seq(AddressSet(0x30000000L, 0x000003ffL)),
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device = dtsdevice,
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concurrency = 1,
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beatBytes = 32/8,
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executable = true
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)
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lazy val module = new MacRegImp(this)
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}
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class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(outer){
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val io: MacRegIO = IO(new MacRegIO)
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val (int, _) = outer.int_node.out(0)
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val RecSmall = RegInit(false.B)
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val Pad = RegInit(true.B)
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val HugEn = RegInit(false.B)
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val CrcEn = RegInit(true.B)
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val DlyCrcEn = RegInit(false.B)
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val Write = io.Cs & Fill(4, io.Rw)
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val Read = io.Cs.orR & ~io.Rw
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val FullD = RegInit(false.B)
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val ExDfrEn = RegInit(false.B)
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val NoBckof = RegInit(false.B)
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val LoopBck = RegInit(false.B)
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val IFG = RegInit(false.B)
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val Pro = RegInit(false.B)
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val Iam = RegInit(false.B)
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val Bro = RegInit(false.B)
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val NoPre = RegInit(false.B)
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val TxEn = RegInit(false.B)
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val RxEn = RegInit(false.B)
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val MODER_Sel = ( io.Address === "h0".U )
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val INT_SOURCE_Sel = ( io.Address === "h1".U )
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val INT_MASK_Sel = ( io.Address === "h2".U )
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val IPGT_Sel = ( io.Address === "h3".U )
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val IPGR1_Sel = ( io.Address === "h4".U )
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val IPGR2_Sel = ( io.Address === "h5".U )
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val PACKETLEN_Sel = ( io.Address === "h6".U )
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val COLLCONF_Sel = ( io.Address === "h7".U )
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val CTRLMODER_Sel = ( io.Address === "h9".U )
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val MIIMODER_Sel = ( io.Address === "hA".U )
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val MIICOMMAND_Sel = ( io.Address === "hB".U )
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val MIIADDRESS_Sel = ( io.Address === "hC".U )
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val MIITX_DATA_Sel = ( io.Address === "hD".U )
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val MAC_ADDR0_Sel = ( io.Address === "h10".U )
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val MAC_ADDR1_Sel = ( io.Address === "h11".U )
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val HASH0_Sel = ( io.Address === "h12".U )
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val HASH1_Sel = ( io.Address === "h13".U )
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val TXCTRL_Sel = ( io.Address === "h14".U )
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val RXCTRL_Sel = ( io.Address === "h15".U )
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val DBG_REG_Sel = ( io.Address === "h16".U )
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val TX_BD_NUM_Sel = ( io.Address === "h8".U )
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val MODER_Wr = Write(2,0) & Fill(3, MODER_Sel)
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val INT_SOURCE_Wr = Write.extract(0) & INT_SOURCE_Sel
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val INT_MASK_Wr = Write.extract(0) & INT_MASK_Sel
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val IPGT_Wr = Write.extract(0) & IPGT_Sel
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val IPGR1_Wr = Write.extract(0) & IPGR1_Sel
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val IPGR2_Wr = Write.extract(0) & IPGR2_Sel
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val PACKETLEN_Wr = Write & Fill(4, PACKETLEN_Sel)
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val COLLCONF_Wr = Cat( Write.extract(2) & COLLCONF_Sel, 0.U(1.W), Write.extract(0) & COLLCONF_Sel)
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val CTRLMODER_Wr = Write.extract(0) & CTRLMODER_Sel
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val MIIMODER_Wr = Write(1,0) & Fill(2, MIIMODER_Sel)
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val MIICOMMAND_Wr = Write.extract(0) & MIICOMMAND_Sel;
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val MIIADDRESS_Wr = Write(1,0) & Fill(2, MIIADDRESS_Sel)
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val MIITX_DATA_Wr = Write(1,0) & Fill(2, MIITX_DATA_Sel)
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val MIIRX_DATA_Wr = io.UpdateMIIRX_DATAReg
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val MAC_ADDR0_Wr = Write & Fill(4, MAC_ADDR0_Sel)
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val MAC_ADDR1_Wr = Write(1,0) & Fill(2, MAC_ADDR1_Sel)
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val HASH0_Wr = Write & Fill(4, HASH0_Sel)
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val HASH1_Wr = Write & Fill(4, HASH1_Sel)
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val TXCTRL_Wr = Write(2,0) & Fill(3, TXCTRL_Sel)
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val TX_BD_NUM_Wr = Write.extract(0) & TX_BD_NUM_Sel & (io.DataIn <= "h80".U)
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val INT_SOURCEOut = Wire(UInt(32.W))
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val MIISTATUSOut = Cat( io.NValid_stat, io.Busy_stat, io.LinkFail )
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// Interrupt generation
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val irq_txb = RegInit(false.B)
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val irq_txe = RegInit(false.B)
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val irq_rxb = RegInit(false.B)
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val irq_rxe = RegInit(false.B)
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val irq_busy = RegInit(false.B)
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val irq_txc = RegInit(false.B)
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val irq_rxc = RegInit(false.B)
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val MODEROut = Cat( // MODER Register
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RegEnable( io.DataIn.extract(16), 0.U(1.W), MODER_Wr.extract(2) ),
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RegEnable( io.DataIn(15,8), "hA0".U(8.W), MODER_Wr.extract(1) ),
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RegEnable( io.DataIn( 7,0), 0.U(8.W), MODER_Wr.extract(0) ),
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)
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val INT_MASK = RegInit(0.U(7.W)) // INT_MASK Register
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val IPGT = RegInit("h12".U(7.W)) // IPGT Register
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val IPGR1 = RegInit("h0C".U(7.W)) // IPGR1 Register
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val IPGR2 = RegInit("h12".U(7.W))
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val maxFL = RegInit("h0600".U(16.W))
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val minFL = RegInit("h0040".U(16.W))
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val collValid = RegInit("h3f".U(6.W))
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val maxRet = RegInit("hF".U(4.U))
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val TX_BD_NUM = RegInit("h40".U(8.W)) // TX_BD_NUM Register
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val txFlow = RegInit(false.B)
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val rxFlow = RegInit(false.B)
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val passAll = RegInit(false.B)
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val clkDiv = RegInit("h64".U(8.W))
|
||||
val miiNoPre = RegInit(false.B)
|
||||
|
||||
|
||||
val INT_MASKOut = RegEnable(io.DataIn(6,0), 0.U(7.W), INT_MASK_Wr) // INT_MASK Register
|
||||
val IPGTOut = RegEnable(io.DataIn(6,0), "h12".U(7.W), IPGT_Wr ) // IPGT Register
|
||||
val IPGR1Out = RegEnable(io.DataIn(6,0), "h0C".U(7.W), IPGR1_Wr) // IPGR1 Register
|
||||
val IPGR2Out = RegEnable(io.DataIn(6,0), "h12".U(7.W), IPGR2_Wr)
|
||||
val scanStat = RegInit(false.B)
|
||||
val readStat = RegInit(false.B)
|
||||
val wCtrlData = RegInit(false.B)
|
||||
|
||||
when(io.RStatStart){ readStat := false.B }
|
||||
when(io.WCtrlDataStart){ wCtrlData := false.B }
|
||||
|
||||
val PACKETLENOut = Cat( // PACKETLEN Register
|
||||
RegEnable(io.DataIn(31,24), 0.U(8.W), PACKETLEN_Wr.extract(3)),
|
||||
RegEnable(io.DataIn(23,16), "h40".U(8.W), PACKETLEN_Wr.extract(2)),
|
||||
RegEnable(io.DataIn(15,8 ), 6.U(8.W), PACKETLEN_Wr.extract(1)),
|
||||
RegEnable(io.DataIn( 7,0 ), 0.U(8.W), PACKETLEN_Wr.extract(0))
|
||||
)
|
||||
val FIAD = RegInit(0.U(5.W))
|
||||
val RGAD = RegInit(0.U(5.W))
|
||||
|
||||
val COLLCONFOut = Cat( // COLLCONF Register
|
||||
RegEnable(io.DataIn(19,16), "hF".U(4.W), COLLCONF_Wr.extract(2)),
|
||||
0.U(10.W),
|
||||
RegEnable(io.DataIn(5,0), "h3f".U(6.W), COLLCONF_Wr.extract(0))
|
||||
)
|
||||
val MIITX_DATA = RegInit(0.U(16.W)) // MIITX_DATA Register
|
||||
|
||||
val TX_BD_NUMOut = RegEnable(io.DataIn(7,0), "h40".U(8.W), TX_BD_NUM_Wr) // TX_BD_NUM Register
|
||||
val CTRLMODEROut = RegEnable(io.DataIn(2,0), 0.U(3.W), CTRLMODER_Wr.extract(0)) // CTRLMODER Register
|
||||
val MIIRX_DATA = RegEnable(io.Prsd, 0.U(16.W), io.UpdateMIIRX_DATAReg) // MIIRX_DATA Register
|
||||
|
||||
val MIIMODEROut = Cat( // MIIMODER Register
|
||||
RegEnable(io.DataIn.extract(8), 0.U(1.W), MIIMODER_Wr.extract(1)),
|
||||
RegEnable(io.DataIn(7,0), "h64".U(8.W), MIIMODER_Wr.extract(0))
|
||||
)
|
||||
val Mac_ADDR0 = RegInit(0.U(32.W))
|
||||
val Mac_ADDR1 = RegInit(0.U(16.W))
|
||||
|
||||
val MIICOMMANDOut0 = RegEnable(io.DataIn.extract(0), 0.U(1.W), MIICOMMAND_Wr)
|
||||
val MIICOMMANDOut1 = RegInit(false.B)
|
||||
val MIICOMMANDOut2 = RegInit(false.B)
|
||||
val HASH0 = RegInit(0.U(32.W))
|
||||
val HASH1 = RegInit(0.U(32.W))
|
||||
|
||||
when(io.RStatStart){
|
||||
MIICOMMANDOut1 := false.B
|
||||
} .elsewhen(MIICOMMAND_Wr){
|
||||
MIICOMMANDOut1 := io.DataIn.extract(1)
|
||||
}
|
||||
val txPauseRq = RegInit(false.B)
|
||||
val txPauseTV = RegInit(0.U(16.W))
|
||||
|
||||
when(io.WCtrlDataStart){
|
||||
MIICOMMANDOut2 := false.B
|
||||
} .elsewhen(MIICOMMAND_Wr){
|
||||
MIICOMMANDOut2 := io.DataIn.extract(2)
|
||||
}
|
||||
val MIICOMMANDOut = Cat(MIICOMMANDOut2, MIICOMMANDOut1, MIICOMMANDOut0) // MIICOMMAND Register
|
||||
|
||||
|
||||
val MIIADDRESSOut = Cat( // MIIADDRESSRegister
|
||||
RegEnable(io.DataIn(12,8), 0.U(5.W), MIIADDRESS_Wr.extract(1)),
|
||||
0.U(3.W),
|
||||
RegEnable(io.DataIn( 4,0), 0.U(5.W), MIIADDRESS_Wr.extract(0))
|
||||
)
|
||||
|
||||
|
||||
val MIITX_DATAOut = Cat( // MIITX_DATA Register
|
||||
RegEnable(io.DataIn(15,8), 0.U(8.W), MIITX_DATA_Wr.extract(1)),
|
||||
RegEnable(io.DataIn( 7,0), 0.U(8.W), MIITX_DATA_Wr.extract(0))
|
||||
)
|
||||
|
||||
val MIIRX_DATAOut = RegEnable(io.Prsd, 0.U(16.W), MIIRX_DATA_Wr) // MIIRX_DATA Register
|
||||
|
||||
val MAC_ADDR0Out = Cat( // MAC_ADDR0 Register
|
||||
RegEnable(io.DataIn(31,24), 0.U(8.W), MAC_ADDR0_Wr.extract(3)),
|
||||
RegEnable(io.DataIn(23,16), 0.U(8.W), MAC_ADDR0_Wr.extract(2)),
|
||||
RegEnable(io.DataIn(15, 8), 0.U(8.W), MAC_ADDR0_Wr.extract(1)),
|
||||
RegEnable(io.DataIn(7 , 0), 0.U(8.W), MAC_ADDR0_Wr.extract(0))
|
||||
)
|
||||
|
||||
val MAC_ADDR1Out = Cat( // MAC_ADDR1 Register
|
||||
RegEnable(io.DataIn(15,8), 0.U(8.W), MAC_ADDR1_Wr.extract(1)),
|
||||
RegEnable(io.DataIn(7 ,0), 0.U(8.W), MAC_ADDR1_Wr.extract(0))
|
||||
)
|
||||
when( io.RstTxPauseRq ){ txPauseRq := false.B }
|
||||
|
||||
|
||||
|
||||
val HASH0Out = Cat( // RXHASH0 Register
|
||||
RegEnable(io.DataIn(31,24), 0.U(8.W), HASH0_Wr.extract(3)),
|
||||
RegEnable(io.DataIn(23,16), 0.U(8.W), HASH0_Wr.extract(2)),
|
||||
RegEnable(io.DataIn(15, 8), 0.U(8.W), HASH0_Wr.extract(1)),
|
||||
RegEnable(io.DataIn(7 , 0), 0.U(8.W), HASH0_Wr.extract(0))
|
||||
)
|
||||
|
||||
val HASH1Out = Cat( // RXHASH1 Register
|
||||
RegEnable(io.DataIn(31,24), 0.U(8.W), HASH1_Wr.extract(3)),
|
||||
RegEnable(io.DataIn(23,16), 0.U(8.W), HASH1_Wr.extract(2)),
|
||||
RegEnable(io.DataIn(15, 8), 0.U(8.W), HASH1_Wr.extract(1)),
|
||||
RegEnable(io.DataIn(7 , 0), 0.U(8.W), HASH1_Wr.extract(0))
|
||||
)
|
||||
|
||||
|
||||
val TXCTRLOut16 = RegInit(false.B)
|
||||
when( io.RstTxPauseRq ){
|
||||
TXCTRLOut16 := false.B
|
||||
} .elsewhen( TXCTRL_Wr.extract(2) ){
|
||||
TXCTRLOut16 := io.DataIn.extract(16)
|
||||
}
|
||||
|
||||
val TXCTRLOut = Cat( // TXCTRL Register
|
||||
TXCTRLOut16,
|
||||
RegEnable(io.DataIn(15,8), 0.U(8.W), TXCTRL_Wr.extract(1)),
|
||||
RegEnable(io.DataIn(7, 0), 0.U(8.W), TXCTRL_Wr.extract(0))
|
||||
)
|
||||
|
||||
|
||||
|
||||
// Reading data from registers
|
||||
io.DataOut :=
|
||||
Mux(
|
||||
Read,
|
||||
Mux1H(Seq(
|
||||
(io.Address === 0.U ) -> MODEROut,
|
||||
(io.Address === 1.U ) -> INT_SOURCEOut,
|
||||
(io.Address === 2.U ) -> INT_MASKOut,
|
||||
(io.Address === 3.U ) -> IPGTOut,
|
||||
(io.Address === 4.U ) -> IPGR1Out,
|
||||
(io.Address === 5.U ) -> IPGR2Out,
|
||||
(io.Address === 6.U ) -> PACKETLENOut,
|
||||
(io.Address === 7.U ) -> COLLCONFOut,
|
||||
(io.Address === 9.U ) -> CTRLMODEROut,
|
||||
(io.Address === 10.U ) -> MIIMODEROut,
|
||||
(io.Address === 11.U ) -> MIICOMMANDOut,
|
||||
(io.Address === 12.U ) -> MIIADDRESSOut,
|
||||
(io.Address === 13.U ) -> MIITX_DATAOut,
|
||||
(io.Address === 14.U ) -> MIIRX_DATAOut,
|
||||
(io.Address === 15.U ) -> MIISTATUSOut,
|
||||
(io.Address === 16.U ) -> MAC_ADDR0Out,
|
||||
(io.Address === 17.U ) -> MAC_ADDR1Out,
|
||||
(io.Address === 8.U ) -> TX_BD_NUMOut,
|
||||
(io.Address === 18.U ) -> HASH0Out,
|
||||
(io.Address === 19.U ) -> HASH1Out,
|
||||
(io.Address === 20.U ) -> TXCTRLOut,
|
||||
(io.Address === 22.U ) -> io.dbg_dat,
|
||||
outer.configNode.regmap(
|
||||
( 0 << 2 ) ->
|
||||
RegFieldGroup("MODER", Some("Mode Register"), Seq(
|
||||
RegField(1, RxEn , RegFieldDesc( "RxEn", "RxEn", reset = Some(0))) ,
|
||||
RegField(1, TxEn , RegFieldDesc( "TxEn", "TxEn", reset = Some(0) ) ),
|
||||
RegField(1, NoPre , RegFieldDesc( "NoPre", "NoPre", reset = Some(0) ) ),
|
||||
RegField(1, Bro , RegFieldDesc( "Bro", "Bro", reset = Some(0) ) ),
|
||||
RegField(1, Iam , RegFieldDesc( "Iam", "Iam", reset = Some(0) ) ),
|
||||
RegField(1, Pro , RegFieldDesc( "Pro", "Pro", reset = Some(0) ) ),
|
||||
RegField(1, IFG , RegFieldDesc( "IFG", "IFG", reset = Some(0) ) ),
|
||||
RegField(1, LoopBck, RegFieldDesc( "LoopBck", "LoopBck", reset = Some(0) ) ),
|
||||
RegField(1, NoBckof, RegFieldDesc( "NoBckof", "NoBckof", reset = Some(0) ) ),
|
||||
RegField(1, ExDfrEn, RegFieldDesc( "ExDfrEn", "ExDfrEn", reset = Some(0) ) ),
|
||||
RegField(1, FullD , RegFieldDesc( "FullD", "FullD", reset = Some(0) ) ),
|
||||
RegField.r(1, 0.U),
|
||||
RegField(1, DlyCrcEn, RegFieldDesc( "DlyCrcEn", "DlyCrcEn", reset=Some(0)) ),
|
||||
RegField(1, CrcEn , RegFieldDesc( "CrcEn", "CrcEn", reset=Some(1)) ),
|
||||
RegField(1, HugEn , RegFieldDesc( "HugEn", "HugEn", reset=Some(0)) ),
|
||||
RegField(1, Pad , RegFieldDesc( "Pad", "Pad", reset=Some(1)) ),
|
||||
RegField(1, RecSmall, RegFieldDesc( "RecSmall", "RecSmall", reset=Some(0)) )
|
||||
)),
|
||||
|
||||
( 1 << 2 ) ->
|
||||
RegFieldGroup("INT_SOURCE", Some("Interrupt Source Register"), Seq(
|
||||
RegField(1, irq_txb, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_txb := 0.U }; true.B }), RegFieldDesc("txb", "txb", reset=Some(0))),
|
||||
RegField(1, irq_txe, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_txe := 0.U }; true.B }), RegFieldDesc("txe", "txe", reset=Some(0))),
|
||||
RegField(1, irq_rxb, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_rxb := 0.U }; true.B }), RegFieldDesc("rxb", "rxb", reset=Some(0))),
|
||||
RegField(1, irq_rxe, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_rxe := 0.U }; true.B }), RegFieldDesc("rxe", "rxe", reset=Some(0))),
|
||||
RegField(1, irq_busy, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_busy := 0.U }; true.B }), RegFieldDesc("busy", "busy", reset=Some(0))),
|
||||
RegField(1, irq_txc, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_txc := 0.U }; true.B }), RegFieldDesc("txc", "txc", reset=Some(0))),
|
||||
RegField(1, irq_rxc, RegWriteFn((valid, data) => { when ((valid & data) === 1.U) { irq_rxc := 0.U }; true.B }), RegFieldDesc("rxc", "rxc", reset=Some(0))),
|
||||
)),
|
||||
|
||||
( 2 << 2 ) ->
|
||||
RegFieldGroup("INT_MASK", Some("Interrupt Mask Register"), Seq(
|
||||
RegField(7, INT_MASK)
|
||||
)),
|
||||
|
||||
( 3 << 2 ) ->
|
||||
RegFieldGroup("IPGT", Some("Back to Back Inter Packet Gap Register"), Seq(
|
||||
RegField(7, IPGT, RegFieldDesc("IPGT", "IPGT", reset=Some(0x12)))
|
||||
)),
|
||||
|
||||
( 4 << 2 ) ->
|
||||
RegFieldGroup("IPGR1", Some("Non Back to Back Inter Packet Gap Register 1"), Seq(
|
||||
RegField(7, IPGR1, RegFieldDesc("IPGR1", "IPGR1", reset=Some(0xc)))
|
||||
)),
|
||||
|
||||
( 5 << 2 ) ->
|
||||
RegFieldGroup("IPGR2", Some("Non Back to Back Inter Packet Gap Register 2"), Seq(
|
||||
RegField(7, IPGR2, RegFieldDesc("IPGR2", "IPGR2", reset=Some(0x12)))
|
||||
)),
|
||||
|
||||
( 6 << 2 ) ->
|
||||
RegFieldGroup("PACKETLEN", Some("Packet Length Register"), Seq(
|
||||
RegField(16, maxFL, RegFieldDesc("maxFL", "Maximum Frame Length", reset=Some(0x0600))),
|
||||
RegField(16, minFL, RegFieldDesc("minFL", "Minimum Frame Length", reset=Some(0x0040))),
|
||||
)),
|
||||
( 7 << 2 ) ->
|
||||
RegFieldGroup("COLLCONF", Some("Collision and Retry Configuration Register"), Seq(
|
||||
RegField(6, collValid, RegFieldDesc("collValid", "Collision Valid", reset=Some(0x3f))),
|
||||
RegField.r(10,0.U),
|
||||
RegField(4, maxRet, RegFieldDesc("maxRet", "Maximum Retry", reset=Some(0xf))),
|
||||
)),
|
||||
|
||||
( 8 << 2 ) ->
|
||||
RegFieldGroup("TX_BD_NUM", Some("Transmit BD Number Register"), Seq(
|
||||
RegField(8, TX_BD_NUM, RegFieldDesc("TX_BD_NUM", "TX_BD_NUM", reset=Some(0x40))),
|
||||
)),
|
||||
|
||||
( 9 << 2 ) ->
|
||||
RegFieldGroup("CTRLMODER", Some("Control Module Mode Register"), Seq(
|
||||
RegField(1, passAll, RegFieldDesc("PassAll", "Pass All Receive Frames", reset=Some(0))),
|
||||
RegField(1, rxFlow , RegFieldDesc("RxFlow", "Receive Flow Control", reset=Some(0))),
|
||||
RegField(1, txFlow , RegFieldDesc("TxFlow", "Transmit Flow Control", reset=Some(0))),
|
||||
)),
|
||||
|
||||
( 10 << 2 ) ->
|
||||
RegFieldGroup("MIIMODER", Some("MII Mode Register"), Seq(
|
||||
RegField(8, clkDiv, RegFieldDesc("clkDiv", "Clock Divider", reset=Some(0x64))),
|
||||
RegField(1, miiNoPre, RegFieldDesc("MIINoPre", "NO Preamble", reset=Some(0x0))),
|
||||
)),
|
||||
|
||||
( 11 << 2 ) ->
|
||||
RegFieldGroup("MIICOMMAND", Some("MII Command Register"), Seq(
|
||||
RegField(1, scanStat, RegFieldDesc("scanStat", "Scan Status", reset=Some(0x0))),
|
||||
RegField(1, readStat, RegFieldDesc("readStat", "Read Status", reset=Some(0x0))),
|
||||
RegField(1, wCtrlData, RegFieldDesc("wCtrlData", "Write Control Data", reset=Some(0x0))),
|
||||
)),
|
||||
|
||||
( 12 << 2 ) ->
|
||||
RegFieldGroup("MIIADDRESS", Some("MII Address Register"), Seq(
|
||||
RegField(5, FIAD, RegFieldDesc("FIAD", "PHY Address", reset=Some(0x0))),
|
||||
RegField.r(3 ,0.U),
|
||||
RegField(5, RGAD, RegFieldDesc("RGAD", "Register Address", reset=Some(0x0))),
|
||||
)),
|
||||
|
||||
( 13 << 2 ) ->
|
||||
RegFieldGroup("MIITX_DATA", Some("MII Transmit Data"), Seq(
|
||||
RegField(16, MIITX_DATA)
|
||||
)),
|
||||
|
||||
( 14 << 2 ) ->
|
||||
RegFieldGroup("MIIRX_DATA", Some("MII Receive Data"), Seq(
|
||||
RegField.r(16, MIIRX_DATA)
|
||||
)),
|
||||
|
||||
( 15 << 2 ) ->
|
||||
RegFieldGroup("MIISTATUS", Some("MII Status Register"), Seq(
|
||||
RegField.r(1, io.LinkFail),
|
||||
RegField.r(1, io.Busy_stat),
|
||||
RegField.r(1, io.NValid_stat),
|
||||
)),
|
||||
|
||||
( 16 << 2 ) ->
|
||||
RegFieldGroup("MAC_ADDR0", Some("MAC Address Register 0"), Seq(
|
||||
RegField(32, Mac_ADDR0)
|
||||
)),
|
||||
|
||||
( 17 << 2 ) ->
|
||||
RegFieldGroup("MAC_ADDR1", Some("MAC Address Register 1"), Seq(
|
||||
RegField(16, Mac_ADDR1)
|
||||
)),
|
||||
|
||||
( 18 << 2 ) ->
|
||||
RegFieldGroup("HASH0", Some("HASH Register 0"), Seq(
|
||||
RegField(32, HASH0)
|
||||
)),
|
||||
|
||||
( 19 << 2 ) ->
|
||||
RegFieldGroup("HASH1", Some("HASH Register 1"), Seq(
|
||||
RegField(32, HASH1)
|
||||
)),
|
||||
|
||||
( 20 << 2 ) ->
|
||||
RegFieldGroup("TXCTRL", Some("Tx Control Register"), Seq(
|
||||
RegField(16, txPauseTV, RegFieldDesc("TxPauseTV", "Tx Pause Timer Value", reset=Some(0x0))),
|
||||
RegField(1, txPauseRq, RegFieldDesc("TxPauseRQ", "Tx Pause Request", reset=Some(0x0))),
|
||||
)),
|
||||
0.U
|
||||
)
|
||||
|
||||
|
||||
io.r_RecSmall := MODEROut.extract(16)
|
||||
io.r_Pad := MODEROut.extract(15)
|
||||
io.r_HugEn := MODEROut.extract(14)
|
||||
io.r_CrcEn := MODEROut.extract(13)
|
||||
io.r_DlyCrcEn := MODEROut.extract(12)
|
||||
io.r_FullD := MODEROut.extract(10)
|
||||
io.r_ExDfrEn := MODEROut.extract( 9)
|
||||
io.r_NoBckof := MODEROut.extract( 8)
|
||||
io.r_LoopBck := MODEROut.extract( 7)
|
||||
io.r_IFG := MODEROut.extract( 6)
|
||||
io.r_Pro := MODEROut.extract( 5)
|
||||
io.r_Iam := MODEROut.extract( 4)
|
||||
io.r_Bro := MODEROut.extract( 3)
|
||||
io.r_NoPre := MODEROut.extract( 2)
|
||||
io.r_TxEn := MODEROut.extract( 1) & (TX_BD_NUMOut > 0.U) // Transmission is enabled when there is at least one TxBD.
|
||||
io.r_RxEn := MODEROut.extract( 0) & (TX_BD_NUMOut < "h80".U) // Reception is enabled when there is at least one RxBD.
|
||||
|
||||
io.r_IPGT := IPGTOut
|
||||
io.r_IPGR1 := IPGR1Out
|
||||
io.r_IPGR2 := IPGR2Out
|
||||
io.r_MinFL := PACKETLENOut(31,16)
|
||||
io.r_MaxFL := PACKETLENOut(15, 0)
|
||||
io.r_MaxRet := COLLCONFOut(19,16)
|
||||
io.r_CollValid := COLLCONFOut( 5, 0)
|
||||
io.r_TxFlow := CTRLMODEROut.extract(2)
|
||||
io.r_RxFlow := CTRLMODEROut.extract(1)
|
||||
io.r_PassAll := CTRLMODEROut.extract(0)
|
||||
io.r_MiiNoPre := MIIMODEROut.extract(8)
|
||||
io.r_ClkDiv := MIIMODEROut(7,0)
|
||||
io.r_WCtrlData := MIICOMMANDOut.extract(2)
|
||||
io.r_RStat := MIICOMMANDOut.extract(1)
|
||||
io.r_ScanStat := MIICOMMANDOut.extract(0)
|
||||
io.r_RGAD := MIIADDRESSOut(12,8)
|
||||
io.r_FIAD := MIIADDRESSOut( 4,0)
|
||||
io.r_CtrlData := MIITX_DATAOut(15,0)
|
||||
|
||||
io.r_MAC := Cat( MAC_ADDR1Out(15,0), MAC_ADDR0Out(31,0) )
|
||||
io.r_HASH1 := HASH1Out
|
||||
io.r_HASH0 := HASH0Out
|
||||
io.r_TxBDNum := TX_BD_NUMOut
|
||||
io.r_TxPauseTV := TXCTRLOut(15,0)
|
||||
io.r_TxPauseRq := TXCTRLOut.extract(16)
|
||||
|
||||
io.r_RecSmall := RecSmall
|
||||
io.r_Pad := Pad
|
||||
io.r_HugEn := HugEn
|
||||
io.r_CrcEn := CrcEn
|
||||
io.r_DlyCrcEn := DlyCrcEn
|
||||
io.r_FullD := FullD
|
||||
io.r_ExDfrEn := ExDfrEn
|
||||
io.r_NoBckof := NoBckof
|
||||
io.r_LoopBck := LoopBck
|
||||
io.r_IFG := IFG
|
||||
io.r_Pro := Pro
|
||||
io.r_Iam := Iam
|
||||
io.r_Bro := Bro
|
||||
io.r_NoPre := NoPre
|
||||
io.r_TxEn := TxEn & (TX_BD_NUM > 0.U) // Transmission is enabled when there is at least one TxBD.
|
||||
io.r_RxEn := RxEn & (TX_BD_NUM < "h80".U) // Reception is enabled when there is at least one RxBD.
|
||||
|
||||
io.r_IPGT := IPGT
|
||||
io.r_IPGR1 := IPGR1
|
||||
io.r_IPGR2 := IPGR2
|
||||
io.r_MinFL := minFL
|
||||
io.r_MaxFL := maxFL
|
||||
io.r_MaxRet := maxRet
|
||||
io.r_CollValid := collValid
|
||||
io.r_TxFlow := txFlow
|
||||
io.r_RxFlow := rxFlow
|
||||
io.r_PassAll := passAll
|
||||
io.r_MiiNoPre := miiNoPre
|
||||
io.r_ClkDiv := clkDiv
|
||||
io.r_WCtrlData := wCtrlData
|
||||
io.r_RStat := readStat
|
||||
io.r_ScanStat := scanStat
|
||||
io.r_RGAD := RGAD
|
||||
io.r_FIAD := FIAD
|
||||
io.r_CtrlData := MIITX_DATA
|
||||
|
||||
io.r_MAC := Cat( Mac_ADDR1(15,0), Mac_ADDR0(31,0) )
|
||||
io.r_HASH1 := HASH1
|
||||
io.r_HASH0 := HASH0
|
||||
io.r_TxBDNum := TX_BD_NUM
|
||||
io.r_TxPauseTV := txPauseTV
|
||||
io.r_TxPauseRq := txPauseRq
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val SetTxCIrq_txclk_wire = Wire(Bool())
|
||||
@@ -331,63 +406,17 @@ class MacReg extends Module{
|
||||
val SetRxCIrq_sync3 = RegNext(SetRxCIrq_sync2, false.B)
|
||||
val SetRxCIrq = RegNext(SetRxCIrq_sync2 & ~SetRxCIrq_sync3, false.B)
|
||||
|
||||
when(io.TxB_IRQ){ irq_txb := true.B }
|
||||
when(io.TxE_IRQ){ irq_txe := true.B }
|
||||
when(io.RxB_IRQ){ irq_rxb := true.B }
|
||||
when(io.RxE_IRQ){ irq_rxe := true.B }
|
||||
when(io.Busy_IRQ){ irq_busy := true.B }
|
||||
when(SetTxCIrq){ irq_txc := true.B }
|
||||
when(SetRxCIrq){ irq_rxc := true.B }
|
||||
|
||||
|
||||
// Interrupt generation
|
||||
val irq_txb = RegInit(false.B)
|
||||
val irq_txe = RegInit(false.B)
|
||||
val irq_rxb = RegInit(false.B)
|
||||
val irq_rxe = RegInit(false.B)
|
||||
val irq_busy = RegInit(false.B)
|
||||
val irq_txc = RegInit(false.B)
|
||||
val irq_rxc = RegInit(false.B)
|
||||
|
||||
|
||||
when(io.TxB_IRQ){
|
||||
irq_txb := true.B
|
||||
}.elsewhen(INT_SOURCE_Wr & io.DataIn.extract(0)){
|
||||
irq_txb := false.B
|
||||
}
|
||||
|
||||
when(io.TxE_IRQ){
|
||||
irq_txe := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(1)){
|
||||
irq_txe := false.B
|
||||
}
|
||||
|
||||
|
||||
when(io.RxB_IRQ){
|
||||
irq_rxb := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(2)){
|
||||
irq_rxb := false.B
|
||||
}
|
||||
|
||||
|
||||
when(io.RxE_IRQ){
|
||||
irq_rxe := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(3)){
|
||||
irq_rxe := false.B
|
||||
}
|
||||
|
||||
when(io.Busy_IRQ){
|
||||
irq_busy := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(4)){
|
||||
irq_busy := false.B
|
||||
}
|
||||
|
||||
|
||||
when(SetTxCIrq){
|
||||
irq_txc := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(5)){
|
||||
irq_txc := false.B
|
||||
}
|
||||
|
||||
when(SetRxCIrq){
|
||||
irq_rxc := true.B
|
||||
} .elsewhen(INT_SOURCE_Wr & io.DataIn.extract(6)){
|
||||
irq_rxc := false.B
|
||||
}
|
||||
|
||||
|
||||
withClockAndReset( io.TxClk.asClock, reset ) {
|
||||
// val ResetTxCIrq_sync1 = Reg(Bool())
|
||||
@@ -422,17 +451,16 @@ class MacReg extends Module{
|
||||
|
||||
|
||||
// Generating interrupt signal
|
||||
io.int_o :=
|
||||
(irq_txb & INT_MASKOut.extract(0) ) |
|
||||
(irq_txe & INT_MASKOut.extract(1) ) |
|
||||
(irq_rxb & INT_MASKOut.extract(2) ) |
|
||||
(irq_rxe & INT_MASKOut.extract(3) ) |
|
||||
(irq_busy & INT_MASKOut.extract(4) ) |
|
||||
(irq_txc & INT_MASKOut.extract(5) ) |
|
||||
(irq_rxc & INT_MASKOut.extract(6) )
|
||||
// io.int_o :=
|
||||
int(0) :=
|
||||
(irq_txb & INT_MASK.extract(0) ) |
|
||||
(irq_txe & INT_MASK.extract(1) ) |
|
||||
(irq_rxb & INT_MASK.extract(2) ) |
|
||||
(irq_rxe & INT_MASK.extract(3) ) |
|
||||
(irq_busy & INT_MASK.extract(4) ) |
|
||||
(irq_txc & INT_MASK.extract(5) ) |
|
||||
(irq_rxc & INT_MASK.extract(6) )
|
||||
|
||||
// For reading interrupt status
|
||||
INT_SOURCEOut := Cat( irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb )
|
||||
|
||||
|
||||
}
|
||||
|
||||
@@ -80,8 +80,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
|
||||
val r_TxEn = Input(Bool()) // Transmit enable
|
||||
val r_RxEn = Input(Bool()) // Receive enable
|
||||
val r_TxBDNum = Input(UInt(8.W)) // Receive buffer descriptor number
|
||||
val RegDataOut = Input(UInt(32.W))
|
||||
val RegCs = Output(UInt(4.W))
|
||||
|
||||
// Interrupts
|
||||
val TxB_IRQ = Output(Bool())
|
||||
@@ -994,7 +992,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
|
||||
|
||||
|
||||
|
||||
io.RegCs := Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & ~io.tlSlv.A.bits.address(11) & ~io.tlSlv.A.bits.address(10)) & io.tlSlv.A.bits.mask // 0x0 - 0x3FF
|
||||
|
||||
BDCs := Fill(4, io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & ~io.tlSlv.A.bits.address(11) & io.tlSlv.A.bits.address(10)) & io.tlSlv.A.bits.mask // 0x400 - 0x7FF
|
||||
CsMiss := io.tlSlv.A.valid & io.tlSlv.A.bits.mask.orR & io.tlSlv.A.bits.address(11) // 0x800 - 0xfFF // When access to the address between 0x800 and 0xfff occurs, acknowledge is set but data is not valid.
|
||||
|
||||
@@ -1008,7 +1006,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
|
||||
slvDValid := false.B
|
||||
} .elsewhen(io.tlSlv.A.fire){
|
||||
slvDValid := true.B
|
||||
slvDDat := Mux( ((io.RegCs.orR) & io.tlSlv.A.bits.opcode === 4.U), io.RegDataOut, BD_WB_DAT_O )
|
||||
slvDDat := BD_WB_DAT_O
|
||||
}
|
||||
|
||||
when(slvAInfo.opcode === 4.U) {
|
||||
@@ -1017,7 +1015,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
|
||||
io.tlSlv.D.bits := edgeIn.AccessAck(slvAInfo)
|
||||
}
|
||||
|
||||
io.tlSlv.A.ready := RegNext(io.RegCs.orR & ~io.tlSlv.A.fire, false.B) | BDAck
|
||||
io.tlSlv.A.ready := BDAck
|
||||
assert( ~(io.tlSlv.A.ready & ~io.tlSlv.A.valid) )
|
||||
|
||||
when( io.tlSlv.A.fire & (~(io.tlSlv.A.bits.mask.orR) | CsMiss) ){
|
||||
|
||||
@@ -12,10 +12,11 @@ trait WithManyMacMix { this: BaseSubsystem =>
|
||||
|
||||
val mac0 = LazyModule(new Mac)
|
||||
|
||||
fbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
|
||||
mbus.coupleTo("mac_cfg") { mac0.tlMasterNode := TLFragmenter(pbus) := _ }
|
||||
mbus.coupleFrom("mac_mst") { _ := TLBuffer() := mac0.tlClientNode }
|
||||
pbus.coupleTo("mac_cfg") { mac0.tlMasterNode := TLFragmenter(pbus) := _ }
|
||||
pbus.coupleTo("mac_cfg") { mac0.ethReg.configNode := TLFragmenter(pbus) := _ }
|
||||
|
||||
ibus.fromSync := mac0.int_node
|
||||
ibus.fromSync := mac0.ethReg.int_node
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -60,7 +60,7 @@ class MacAXI(implicit p: Parameters) extends Mac{
|
||||
|
||||
|
||||
tlMasterNode := xbar := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := axiConfigPort
|
||||
tlError.node := xbar
|
||||
// tlError.node := xbar
|
||||
|
||||
val intSinkNode = IntSinkNode(IntSinkPortSimple())
|
||||
intSinkNode := int_node
|
||||
@@ -37,11 +37,13 @@ class MacTest(implicit p: Parameters) extends Mac{
|
||||
))
|
||||
)))
|
||||
|
||||
tlMasterNode := tlClientIONode
|
||||
val tlBar = TLXbar()
|
||||
|
||||
tlMasterNode := tlBar := tlClientIONode
|
||||
ethReg.configNode := tlBar
|
||||
|
||||
val intSinkNode = IntSinkNode(IntSinkPortSimple())
|
||||
intSinkNode := int_node
|
||||
intSinkNode := ethReg.int_node
|
||||
|
||||
val tlSlv = InModuleBody {
|
||||
tlClientIONode.makeIOs()
|
||||
|
||||
@@ -19,7 +19,7 @@ object testModule extends App {
|
||||
|
||||
(new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
|
||||
ChiselGeneratorAnnotation(() => {
|
||||
val soc = LazyModule(new MacAXI()(cfg))
|
||||
val soc = LazyModule(new MacTest()(cfg))
|
||||
soc.module
|
||||
})
|
||||
))
|
||||
|
||||
Reference in New Issue
Block a user