compile pass

2023-07-20 14:58:59 +08:00
parent fa748b7de9
commit 0b48e2cd2b
7 changed files with 432 additions and 415 deletions
--- a/src/test/scala/gcd/Mac_test_top.scala
+++ b/src/test/scala/gcd/Mac_test_top.scala
@@ -37,11 +37,13 @@ class MacTest(implicit p: Parameters) extends Mac{
 			))
 		)))

-	tlMasterNode := tlClientIONode
+		val tlBar = TLXbar()

+	tlMasterNode := tlBar := tlClientIONode
+	ethReg.configNode  := tlBar

 	val intSinkNode = IntSinkNode(IntSinkPortSimple())
-	intSinkNode := int_node
+	intSinkNode := ethReg.int_node

    val tlSlv = InModuleBody {
      tlClientIONode.makeIOs()