compile pass

src/test/scala/gcd/MacAXI.scala.bk

@@ -60,7 +60,7 @@ class MacAXI(implicit p: Parameters) extends Mac{
 
 
 	tlMasterNode := xbar := AXI4ToTL() := AXI4UserYanker(Some(1)) := AXI4Fragmenter() := axiConfigPort
-  tlError.node := xbar
+  // tlError.node := xbar
 
 	val intSinkNode = IntSinkNode(IntSinkPortSimple())
 	intSinkNode := int_node

src/test/scala/gcd/Mac_test_top.scala

@@ -37,11 +37,13 @@ class MacTest(implicit p: Parameters) extends Mac{
 			))
 		)))
 
-	tlMasterNode := tlClientIONode
+		val tlBar = TLXbar()
 
+	tlMasterNode := tlBar := tlClientIONode
+	ethReg.configNode  := tlBar
 
 	val intSinkNode = IntSinkNode(IntSinkPortSimple())
-	intSinkNode := int_node
+	intSinkNode := ethReg.int_node
 
     val tlSlv = InModuleBody {
       tlClientIONode.makeIOs()

src/test/scala/gcd/test.scala

@@ -19,7 +19,7 @@ object testModule extends App {
 
   (new chisel3.stage.ChiselStage).execute( Array("--show-registrations", "--full-stacktrace", "--target-dir", "generated/Main") ++ args, Seq(
       ChiselGeneratorAnnotation(() => {
-    val soc = LazyModule(new MacAXI()(cfg))
+    val soc = LazyModule(new MacTest()(cfg))
     soc.module
   })
   ))