diff --git a/tb/shinTest/Makefile_vcs b/tb/shinTest/Makefile_vcs
index 70ff0e6..9998fe8 100644
--- a/tb/shinTest/Makefile_vcs
+++ b/tb/shinTest/Makefile_vcs
@@ -12,6 +12,8 @@ SIM = ./${OUTPUT} -l run.log
 
 testShin_vcs:
 	python3 ./shinTest/gen_pkt.py
+	mkdir -p generated/log
+	rm -rf generated/log/*
 	${VCS} -f ./shinTest_vcs.f
 	${SIM}
 sim:
diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py
index dc6ae45..fd0e550 100755
--- a/tb/shinTest/gen_pkt.py
+++ b/tb/shinTest/gen_pkt.py
@@ -76,7 +76,6 @@ if __name__ == '__main__':
     #add_tc_2_runlist(base.tc27())
     #add_tc_2_runlist(base.tc28())
     #add_tc_2_runlist(base.tc29())
-    #add_tc_2_runlist(base.tc29())
     #add_tc_2_runlist(base.tc30())
 
 
diff --git a/tb/shinTest/shinTest_vcs.f b/tb/shinTest/shinTest_vcs.f
index 4e016b9..8e99223 100644
--- a/tb/shinTest/shinTest_vcs.f
+++ b/tb/shinTest/shinTest_vcs.f
@@ -1,28 +1,5 @@
 +incdir+./generated/shin
 ./shinTest/ShinTopSpiTb.v
-./generated/SimCDR/Queue.v
-./generated/SimCDR/b8b10Encode.v
-./generated/SimCDR/b8b10Decode.v
-./generated/SimCDR/CDROut.v
-./generated/SimCDR/CDRInMultiSample.v
-./generated/SimCDR/MPCDRIn.v
-./generated/SimCDR/SimCDR.v
-./generated/SimCDR/CDRInAxis.v
-./generated/back/do16p_top.v
-./generated/back/SpiSRAMUp.v
-./generated/back/di16_top.v
-./generated/back/MirrorSRAMDP.v
-./generated/back/spi_top.v
-./generated/back/BackBoardMst.v
-./generated/back/backBoardMstTop.v
-./generated/back/oser_rst.v
-./generated/back/do16c_top.v
-./generated/back/DOut16c.v
-./generated/back/SpiSRAMDown.v
-./generated/back/DOut16p.v
-./generated/back/defineParam.v
-./generated/back/DIn16.v
-./generated/back/SpiSlv.v
 ./generated/shin/b4b5DualEncode.v
 ./generated/shin/ShareSRAM2k.v
 ./generated/shin/QSpiInterface.v
diff --git a/tb/shinTest/testcase/environment.py b/tb/shinTest/testcase/environment.py
index 849c547..769c848 100644
--- a/tb/shinTest/testcase/environment.py
+++ b/tb/shinTest/testcase/environment.py
@@ -249,18 +249,18 @@ def __gen_slv_dev_predef(num):
                 +"`define SPI_CSN_NUM          (`ALL_DEV_NUM * 3)\n"
 
                 +"`define HW_SERIAL            48'h31303050584c //(48'h4c5850303031)\n"
-                +"`define IQSPI_PINS(N)        (`N*4+3):(`N*4)\n"
-                +"`define EQSPI_PINS(N)        ((`N + `ALL_DEV_NUM)*4+3):((`N + `ALL_DEV_NUM)*4)\n"
-                +"`define IQSPI_MISO(N)        qspi_miso[`IQSPI_PINS(`N)]\n"
-                +"`define EQSPI_MISO(N)        qspi_miso[`EQSPI_PINS(`N)]\n"
+                +"`define IQSPI_PINS(N)        (N*4+3):(N*4)\n"
+                +"`define EQSPI_PINS(N)        ((N + `ALL_DEV_NUM)*4+3):((N + `ALL_DEV_NUM)*4)\n"
+                +"`define IQSPI_MISO(N)        qspi_miso[`IQSPI_PINS(N)]\n"
+                +"`define EQSPI_MISO(N)        qspi_miso[`EQSPI_PINS(N)]\n"
 
-                +"`define IQSPI_CSN_NUM(id)    (`id)\n"
-                +"`define ESPI_CSN_NUM(id)     ((`id)+(`ALL_DEV_NUM))\n"
-                +"`define EQSPI_CSN_NUM(id)    ((`id)+(`ALL_DEV_NUM)*2)\n"
+                +"`define IQSPI_CSN_NUM(id)    (id)\n"
+                +"`define ESPI_CSN_NUM(id)     ((id)+(`ALL_DEV_NUM))\n"
+                +"`define EQSPI_CSN_NUM(id)    ((id)+(`ALL_DEV_NUM)*2)\n"
 
-                +"`define IQSPI_CSN(id)        spi_csn[`IQSPI_CSN_NUM(`id)]\n"
-                +"`define ESPI_CSN(id)         spi_csn[`ESPI_CSN_NUM(`id)]\n"
-                +"`define EQSPI_CSN(id)        spi_csn[`EQSPI_CSN_NUM(`id)]\n"
+                +"`define IQSPI_CSN(id)        spi_csn[`IQSPI_CSN_NUM(id)]\n"
+                +"`define ESPI_CSN(id)         spi_csn[`ESPI_CSN_NUM(id)]\n"
+                +"`define EQSPI_CSN(id)        spi_csn[`EQSPI_CSN_NUM(id)]\n"
                 )
     
     code_qspi_mux_init = "`define QSPI_MUX_MISO_INIT    \\\n"