From 0ae44e5c68f50087a47698384fa63c7c1739ec1b Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Mon, 18 Mar 2024 20:01:43 +0800
Subject: [PATCH] =?UTF-8?q?FSMC=E5=86=99=E4=BC=98=E5=8C=96=E5=90=8E?=
 =?UTF-8?q?=E9=80=9A=E8=BF=87?=
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---
 src/main/scala/backBoard/BackBoardMst.scala | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index f1d8f34..fe3181c 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -176,17 +176,19 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     ))
 
 
-  
+    val isNewWR = RegInit(false.B)
 
     when( isAccessReg & fsmcCSSync(1) & fsmcWRSync(1) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
-
-      isRegRefleshFlip := ~isRegRefleshFlip
+      isNewWR := true.B
       wrRegAddr        := activeAddr
       wrRegData        := io.FSMC.ADIn
 
     }
 
-
+    when( fsmcCSSync(2) & ~fsmcCSSync(1) & isNewWR ){
+      isNewWR := false.B
+      isRegRefleshFlip := ~isRegRefleshFlip
+    }
 
   }