diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index f1d8f34..fe3181c 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -176,17 +176,19 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     ))
 
 
-  
+    val isNewWR = RegInit(false.B)
 
     when( isAccessReg & fsmcCSSync(1) & fsmcWRSync(1) ){ //~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
-
-      isRegRefleshFlip := ~isRegRefleshFlip
+      isNewWR := true.B
       wrRegAddr        := activeAddr
       wrRegData        := io.FSMC.ADIn
 
     }
 
-
+    when( fsmcCSSync(2) & ~fsmcCSSync(1) & isNewWR ){
+      isNewWR := false.B
+      isRegRefleshFlip := ~isRegRefleshFlip
+    }
 
   }