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脉冲电平spi清零测试完成

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Ruige Lee
2025-05-16 16:42:07 +08:00
parent 58fbbdd1fc
commit 0a772e4efc
1 changed files with 33 additions and 7 deletions
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40
tb/shinTest/ShinTopSpiTb.v
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@@ -666,16 +666,29 @@ initial begin
txBuf[10+3] = 8'h0; //工作计数0
txBuf[11+3] = 8'h0; //工作计数0
txBuf[12+3] = 8'h0f; //负载0x120 0x0f 全部脉冲，全部使能
// txBuf[12+3] = 8'h0f; //负载0x120 0x0f 全部脉冲，全部使能
// txBuf[13+3] = 0; //负载0x121
// txBuf[14+3] = 10; //负载0x122 sync0脉冲宽度 10
// txBuf[15+3] = 0; //负载0x123
// txBuf[16+3] = 0; //负载0x124 sync1脉冲宽度 0
// txBuf[17+3] = 0; //负载0x125
// txBuf[18+3] = 1; //负载0x126 sync2脉冲宽度 1
// txBuf[19+3] = 0; //负载0x127
// txBuf[20+3] = 8'hff; //负载0x128 sync3脉冲宽度 最大
// txBuf[21+3] = 8'hff; //负载0x129
txBuf[12+3] = 8'hff; //负载0x120 0xff 全部电平，全部使能
txBuf[13+3] = 0; //负载0x121
txBuf[14+3] = 10; //负载0x122 sync0脉冲宽度 10
txBuf[14+3] = 0; //负载0x122 sync0脉冲宽度
txBuf[15+3] = 0; //负载0x123
txBuf[16+3] = 0; //负载0x124 sync1脉冲宽度 0
txBuf[16+3] = 0; //负载0x124 sync1脉冲宽度
txBuf[17+3] = 0; //负载0x125
txBuf[18+3] = 1; //负载0x126 sync2脉冲宽度 1
txBuf[18+3] = 0; //负载0x126 sync2脉冲宽度
txBuf[19+3] = 0; //负载0x127
txBuf[20+3] = 8'hff; //负载0x128 sync3脉冲宽度 最大
txBuf[21+3] = 8'hff; //负载0x129
txBuf[20+3] = 0; //负载0x128 sync3脉冲宽度
txBuf[21+3] = 0; //负载0x129
txBuf[22+3] = 0; //负载0x12a empty
txBuf[23+3] = 0; //负载0x12b
@@ -696,7 +709,7 @@ initial begin
//周期
txBuf[36+3] = 8'hff; //负载0x138
txBuf[37+3] = 0; //负载0x139
txBuf[37+3] = 8'hf; //负载0x139
txBuf[38+3] = 0; //负载0x13a
txBuf[39+3] = 0; //负载0x13b
@@ -732,6 +745,19 @@ initial begin
end
//清脉冲
//设置SM1在写入19地址触发enq
txBuf[0+3] = 0; //负载0x122 sync0脉冲宽度
txBuf[1+3] = 0; //负载0x123
txBuf[2+3] = 0; //负载0x124 sync1脉冲宽度
txBuf[3+3] = 0; //负载0x125
txBuf[4+3] = 0; //负载0x126 sync2脉冲宽度
txBuf[5+3] = 0; //负载0x127
txBuf[6+3] = 0; //负载0x128 sync3脉冲宽度
txBuf[7+3] = 0; //负载0x129
spi_trans( (16'h0122), (`SPI_WRITE), (8), (2) ); //slv2
end